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: Submitter =
Bin.Cheng
| State =
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| 133 patches
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«
1
2
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
Refactor force_expr_to_var_cost and handle type conversion
- - - -
-
-
-
2013-11-11
Bin.Cheng
New
[Ping] Two pending IVOPT patches
- - - -
-
-
-
2014-01-11
Bin.Cheng
New
Pick up more address lowering cases for ivopt and tree-affine.c
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-
-
-
2014-05-06
Bin.Cheng
New
[AARCH64] Support full addressing modes for ldr/str in vectorization scenarios
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-
-
-
2014-05-28
Bin.Cheng
New
Enable elimination of IV use with unsigned type candidate
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-
-
-
2014-07-01
Bin.Cheng
New
[ARM] Improve ARM memset inlining
- - - -
-
-
-
2014-07-08
Bin.Cheng
New
[1/3] Improve induction variable elimination
- - - -
-
-
-
2014-07-21
Bin.Cheng
New
[3/3] Improve induction variable elimination
- - - -
-
-
-
2014-07-21
Bin.Cheng
New
[3/3] Improve induction variable elimination
- - - -
-
-
-
2014-07-21
Bin.Cheng
New
[ARM] Improve ARM memset inlining
- - - -
-
-
-
2014-07-21
Bin.Cheng
New
[2/3] Improve induction variable elimination
- - - -
-
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-
2014-08-06
Bin.Cheng
New
[2/3] Improve induction variable elimination
- - - -
-
-
-
2014-08-14
Bin.Cheng
New
[RFC] Fix latent bug in combine pass as reported in pr62151
- - - -
-
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-
2014-08-18
Bin.Cheng
New
Cleanup interface of iv_ca_add_use and the calls to it
- - - -
-
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-
2014-08-27
Bin.Cheng
New
[PR62151] Fix uninitialized register issue caused by distribute_notes in combine pass
- - - -
-
-
-
2014-08-28
Bin.Cheng
New
[RFC] Pair load store instructions using a generic scheduling fusion pass
- - - -
-
-
-
2014-11-05
Bin.Cheng
New
[RFC] Pair load store instructions using a generic scheduling fusion pass
- - - -
-
-
-
2014-11-14
Bin.Cheng
New
[PR62178] Improve candidate selecting in IVOPT, 2nd try.
- - - -
-
-
-
2014-12-16
Bin.Cheng
New
[PR62178] Improve candidate selecting in IVOPT, 2nd try.
- - - -
-
-
-
2014-12-16
Bin.Cheng
New
[PR62178] Improve candidate selecting in IVOPT, 2nd try.
- - - -
-
-
-
2014-12-17
Bin.Cheng
New
[PR62151] Fix REG_DEAD note distribution issue by using right ELIM_I0/ELIM_I1
- - - -
-
-
-
2014-12-22
Bin.Cheng
New
[PR62151] Fix REG_DEAD note distribution issue by using right ELIM_I0/ELIM_I1
- - - -
-
-
-
2014-12-22
Bin.Cheng
New
[PR64705] Don't aggressively expand induction variable's base
- - - -
-
-
-
2015-02-12
Bin.Cheng
New
[ARM] Fix memset-inline-* failures on cortex-a9 tune by checking tune information.
- - - -
-
-
-
2015-03-17
Bin.Cheng
New
Improve how we handle overflow for type conversion in scev/ivopts, part I
- - - -
-
-
-
2015-05-24
Bin.Cheng
New
Improve overflow in scev by using information computed in loop niter, part II
- - - -
-
-
-
2015-06-01
Bin.Cheng
New
Improve how we handle overflow in scev by using overflow information computed for control iv in loo…
- - - -
-
-
-
2015-06-02
Bin.Cheng
New
Improve how we handle overflow for type conversion in scev/ivopts, part I
- - - -
-
-
-
2015-06-02
Bin.Cheng
New
Preserve ssa name (thus vrp info) for IV structure. Committed.
- - - -
-
-
-
2015-06-03
Bin.Cheng
New
Improve bound information in loop niter analysis
- - - -
-
-
-
2015-08-17
Bin.Cheng
New
[PR66388] Add sizetype cand for BIV of smaller type if it's used as index of memory ref
- - - -
-
-
-
2015-09-15
Bin.Cheng
New
Improve rtl loop inv cost by checking if the inv can be propagated to address uses
- - - -
-
-
-
2015-10-09
Bin.Cheng
New
Improve rtl loop inv cost by checking if the inv can be propagated to address uses
- - - -
-
-
-
2015-10-21
Bin.Cheng
New
[PR52272] Be smart when adding iv candidates
- - - -
-
-
-
2015-11-10
Bin.Cheng
New
[PR52272] Be smart when adding iv candidates
- - - -
-
-
-
2015-11-10
Bin.Cheng
New
[AArch64] Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- - - -
-
-
-
2015-11-19
Bin.Cheng
New
[PR68529] Fix not recognized scev by computing no-overflow info for loop with NE_EXPR exit condition
- - - -
-
-
-
2015-11-28
Bin.Cheng
New
[AArch64] Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- - - -
-
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-
2015-12-01
Bin.Cheng
New
[AArch64] Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- - - -
-
-
-
2015-12-03
Bin.Cheng
New
[AArch64] Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- - - -
-
-
-
2015-12-04
Bin.Cheng
New
[PR66796] Obvious, revise check condition in test case
- - - -
-
-
-
2016-01-18
Bin.Cheng
New
[PR69052] Check if loop inv can be propagated into mem ref with additional addr expr canonicalizati…
- - - -
-
-
-
2016-02-23
Bin.Cheng
New
[PR69052] Set higher precedence for CONST_WIDE_INT than CONST_INT when canonicalizing addr expr
- - - -
-
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-
2016-03-07
Bin.Cheng
New
Reduce compilation time for IVOPT by skipping cost computation in use group
- - - -
-
-
-
2016-03-30
Bin.Cheng
New
Reduce compilation time for IVOPT by skipping cost computation in use group
- - - -
-
-
-
2016-03-31
Bin.Cheng
New
[PR69489/01] Improve tree ifcvt by storing/tracking DR against its innermost loop bahavior if possi…
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-
-
-
2016-03-31
Bin.Cheng
New
Support BIT_AND_EXPR in scalar evolution
- - - -
-
-
-
2016-04-20
Bin.Cheng
New
Improve tree ifconv by handling virtual PHIs which can be degenerated.
- - - -
-
-
-
2016-04-25
Bin.Cheng
New
Refactor IVOPT.
- - - -
-
-
-
2016-04-27
Bin.Cheng
New
Do more tree if-conversions by handlding PHIs with more than two arguments.
- - - -
-
-
-
2016-04-29
Bin.Cheng
New
Proving no-trappness for array ref in tree if-conv using loop niter information.
- - - -
-
-
-
2016-05-06
Bin.Cheng
New
[PR69848/partial] Propagate comparison into VEC_COND_EXPR if target supports
- - - -
-
-
-
2016-05-16
Bin.Cheng
New
[PR69848/partial] Propagate comparison into VEC_COND_EXPR if target supports
- - - -
-
-
-
2016-05-18
Bin.Cheng
New
A latent alignment bug in tree-ssa-address.c
- - - -
-
-
-
2016-05-23
Bin.Cheng
New
Resolve compilation time known alias checks in vectorizer
- - - -
-
-
-
2016-06-28
Bin.Cheng
New
Improve loop-niter to handle possible infinite loop.
- - - -
-
-
-
2016-07-13
Bin.Cheng
New
Remove support for -funsafe-loop-optimizations
- - - -
-
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-
2016-07-18
Bin.Cheng
New
[PR71503/PR71683] Fix ICE in tree-if-conv.c
- - - -
-
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-
2016-07-19
Bin.Cheng
New
Improve no-overflow check in SCEV using value range info.
- - - -
-
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-
2016-07-20
Bin.Cheng
New
[GCC/01] Bring back warning message on loop whose counter might overflow
- - - -
-
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-
2016-07-22
Bin.Cheng
New
Support constraint flags in loop structure.
- - - -
-
-
-
2016-07-28
Bin.Cheng
New
Simplify interface for simplify_using_initial_conditions
- - - -
-
-
-
2016-08-05
Bin.Cheng
New
[AArch64/V3] Add new patterns for vcond_mask and vec_cmp
- - - -
-
-
-
2016-08-08
Bin.Cheng
New
[v2] Simplify alias check code generation in vectorizer
- - - -
-
-
-
2016-09-22
Bin.Cheng
New
[2/9] Add interface reseting original copy tables in cfg.c
- - - -
-
-
-
2016-10-13
Bin.Cheng
New
[9/9] Prove no-overflow in computation of LOOP_VINFO_NITERS and improve code generation
- - - -
-
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-
2016-10-13
Bin.Cheng
New
[1/4] Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)
- - - -
-
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2016-10-26
Bin.Cheng
New
[3/4] Add support for constant operand in pattern (convert (op:s (convert@2 @0) (convert?@3 @1)))
- - - -
-
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-
2016-10-26
Bin.Cheng
New
[1/4] Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)
- - - -
-
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-
2016-10-26
Bin.Cheng
New
[VECT] Support operand swapping for cond_expr in vect_slp
- - - -
-
-
-
2016-10-31
Bin.Cheng
New
[VECT] Swap operands for cond_reduction when necessary
- - - -
-
-
-
2016-11-01
Bin.Cheng
New
[PR78114] Refine gfortran.dg/vect/fast-math-mgrid-resid.f
- - - -
-
-
-
2016-11-17
Bin.Cheng
New
Refine type conversion in result expressions for cond_expr pattern
- - - -
-
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-
2016-11-23
Bin.Cheng
New
Refine type conversion in result expressions for cond_expr pattern
- - - -
-
-
-
2016-11-24
Bin.Cheng
New
[PR78507/PR78510] Fix two ICEs in pattern (cond (cmp (convert1? @1) @3) (convert2? @1) @2).
- - - -
-
-
-
2016-11-25
Bin.Cheng
New
Simplify (cond (cmp (convert? x) c1) (op x c2) c3) -> (op (minmax x c1) c2)
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-
-
-
2016-12-02
Bin.Cheng
New
[TEST] Add test for PR78652
- - - -
-
-
-
2017-01-13
Bin.Cheng
New
Be careful about combined chain with length == 0 (PR, tree-optimization/70754).
- - - -
-
-
-
2017-01-20
Bin.Cheng
New
[PR79347] Maintain profile counter information in vect_do_peeling
- - - -
-
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-
2017-02-15
Bin.Cheng
New
[PR77536] Generate correct profiling information for vectorized loop
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-
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-
2017-02-21
Bin.Cheng
New
[PR77536] Generate correct profiling information for vectorized loop
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-
-
-
2017-02-22
Bin.Cheng
New
[PR80153] Always generate folded type conversion in tree-affine
- - - -
-
-
-
2017-03-29
Bin.Cheng
New
[PR80153] Always generate folded type conversion in tree-affine
- - - -
-
-
-
2017-03-30
Bin.Cheng
New
[RFC] Fix P1 PR77498
- - - -
-
-
-
2017-03-31
Bin.Cheng
New
[PR80153] Always generate folded type conversion in tree-affine
- - - -
-
-
-
2017-04-05
Bin.Cheng
New
[GCC8,33/33] Fix PR69710/PR68030 by reassociate vect base address and a simple CSE pass
- - - -
-
-
-
2017-04-19
Bin.Cheng
New
[GCC8,13/33] Rewrite cost computation of ivopts
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-
-
2017-04-26
Bin.Cheng
New
[GCC8,22/33] Generate TMR in new reassociation order
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2017-04-26
Bin.Cheng
New
[GCC8,22/33] Generate TMR in new reassociation order
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2017-05-02
Bin.Cheng
New
[GCC8,01/33] Handle TRUNCATE between tieable modes in rtx_cost
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2017-05-03
Bin.Cheng
New
[GCC8,07/33] Offset validity check in address expression
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2017-05-04
Bin.Cheng
New
[GCC8,11/33] New interfaces for tree affine
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2017-05-04
Bin.Cheng
New
[GCC8,13/33] Rewrite cost computation of ivopts
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-
2017-05-04
Bin.Cheng
New
[GCC8,28/33] Don't count non-interger PHIs for register pressure
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-
2017-05-04
Bin.Cheng
New
[GCC8,17/33] Treat complex cand step as invriant expression
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2017-05-04
Bin.Cheng
New
[GCC8,01/33] Handle TRUNCATE between tieable modes in rtx_cost
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2017-05-10
Bin.Cheng
New
[GCC8,29/33] New register pressure estimation
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2017-05-15
Bin.Cheng
New
[GCC8,30/33] Fold more type conversion into binary arithmetic operations
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2017-05-15
Bin.Cheng
New
[GCC8,31/33] Set range information for niter bound of vectorized loop
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2017-05-15
Bin.Cheng
New
[GCC8,31/33] Set range information for niter bound of vectorized loop
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2017-05-22
Bin.Cheng
New
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