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Patch A/R/T Date Submitter Delegate State
[AArch64] Implement some saturating math NEON intrinsics 0 0 0 2014-08-04 Kyrylo Tkachov New
[AArch64] Implement some vca*_f[32,64] intrinsics 0 0 0 2014-07-10 Kyrylo Tkachov New
[AArch64] Implement some vca*_f[32,64] intrinsics 0 0 0 2014-06-23 Kyrylo Tkachov New
[AArch64] Implement some vmul*_lane*_f* intrinsics in arm_neon.h 0 0 0 2014-08-04 Kyrylo Tkachov New
[AArch64] Implement support for LD1R. 0 0 0 2013-01-09 Tejas Belagod New
[AArch64] Implement support for LD{1,2,3,4}/ST{1,2,3,4}. 0 0 0 2012-09-10 Tejas Belagod New
[AArch64] Implement vbsl_f64 arm_neon.h intrinsic 0 0 0 2014-07-16 Kyrylo Tkachov New
[AArch64] Implement vcopy intrinsics. 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Implement vec_init. 0 0 0 2013-01-07 Tejas Belagod New
[AArch64] Implement vector float->double widening and double->float narrowing. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Implement vfma_f64, vmla_f64, vfms_f64, vmls_f64 intrinsics 0 0 0 2014-06-20 Kyrylo Tkachov New
[AArch64] Implement vmovq_n_f64. 0 0 0 2012-09-10 Tejas Belagod New
[AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in C 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Implement vset_lane intrinsics in C 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Implement vsqrt_f64 intrinsic 0 0 0 2014-11-27 Kyrylo Tkachov New
[AArch64] Implement vsqrt_f64 intrinsic 0 0 0 2014-11-17 Kyrylo Tkachov New
[AArch64] Implement workaround for ARM Cortex-A53 erratum 835769 0 0 0 2014-10-10 Kyrylo Tkachov New
[AArch64] Implementent sync gen and atomic builtins. 0 0 0 2012-11-16 James Greenhalgh New
[AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook 0 0 0 2014-08-01 Jiong Wang New
[AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook 0 0 0 2014-08-01 Jiong Wang New
[AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt 0 0 0 2015-07-28 Jiong Wang New
[AArch64] Improve arm_neon.h vml<as>_lane handling. 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber 0 0 0 2015-01-27 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber 0 0 0 2015-01-19 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber 0 0 0 2015-01-19 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber 0 0 0 2014-12-15 Jiong Wang New
[AArch64] Improve csinc/csneg/csinv opportunities on immediates 0 0 0 2015-07-10 Kyrylo Tkachov New
[AArch64] Improve description of <F>CM instructions in RTL 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Improve handling of constants destined for FP_REGS 0 0 0 2013-09-04 Ian Bolton New
[AArch64] Improve spill code - swap order in shl pattern 0 0 0 2015-04-27 Wilco New
[AArch64] Improve spill code - swap order in shr patterns 0 0 0 2015-07-27 Wilco New
[AArch64] Improve vst4_lane intrinsics 0 0 0 2014-02-13 James Greenhalgh New
[AArch64] Increase static buffer size in aarch64_rewrite_selected_cpu 0 0 0 2015-04-20 Kyrylo Tkachov New
[AArch64] LINK_SPEC changes for Cortex-A53 erratum 835769 workaround 0 0 0 2014-10-22 Kyrylo Tkachov New
[AArch64] LR register not used in leaf functions 0 0 0 2014-09-30 Jiong Wang New
[AArch64] LR register not used in leaf functions 0 0 0 2014-09-22 Kugan New
[AArch64] Logical vector shift right conformance 0 0 0 2014-02-25 Alex Velenko New
[AArch64] Make -mcpu, -march and -mtune case-insensitive. 0 0 0 2014-01-17 Alan Lawrence New
[AArch64] Make <su>mull<q> target tests more robust. 0 0 0 2013-01-08 Tejas Belagod New
[AArch64] Make MOVK output operand 2 in hex 0 0 0 2013-03-20 Ian Bolton New
[AArch64] Make aarch64_min_divisions_for_recip_mul configurable 0 0 0 2015-05-01 Wilco New
[AArch64] Make aarch64_min_divisions_for_recip_mul configurable 0 0 0 2015-03-03 Wilco New
[AArch64] Make argument of ld1 intrinsics const. 0 0 0 2013-01-07 James Greenhalgh New
[AArch64] Make gentune.sh also generate "generic_sched" attribute 0 0 0 2014-12-17 James Greenhalgh New
[AArch64] Make gentune.sh also generate "generic_sched" attribute 0 0 0 2014-09-25 James Greenhalgh New
[AArch64] Make integer vabs intrinsics UNSPECs 0 0 0 2015-01-28 James Greenhalgh New
[AArch64] Make omit-frame-pointer work correctly 0 0 0 2013-03-28 Ian Bolton New
[AArch64] Make reduc_* operations bigendian-safe. 0 0 0 2013-11-15 Tejas Belagod New
[AArch64] Make sure start callee-save offset for D registers aligned 0 0 0 2014-06-05 Jiong Wang New
[AArch64] Make vabs<q>_f<32, 64> a tree/gimple intrinsic. 0 0 0 2013-04-25 James Greenhalgh New
[AArch64] Make zero_extends explicit for common SImode patterns 0 0 0 2012-12-14 Ian Bolton New
[AArch64] Make zero_extends explicit for common SImode patterns 0 0 0 2012-12-13 Ian Bolton New
[AArch64] Make zero_extends explicit for some SImode patterns 0 0 0 2013-01-15 Ian Bolton New
[AArch64] Map fcvt intrinsics to builtin name directly. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Map frint intrinsics to standard pattern names directly. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Map standard pattern names to NEON intrinsics directly. 0 0 0 2013-04-22 James Greenhalgh New
[AArch64] Minor refactoring of aarch64_add_offset 0 0 0 2013-06-25 Yufeng Zhang New
[AArch64] Minor refactoring of aarch64_force_temporary 0 0 0 2013-06-25 Yufeng Zhang New
[AArch64] Move immediate into Advanced SIMD scalar. 0 0 0 2012-09-10 Tejas Belagod New
[AArch64] NEON vadd_f64 and vsub_f64 intrinsics modified 0 0 0 2013-10-08 Alex Velenko New
[AArch64] NEON vclz intrinsic modified 0 0 0 2013-10-08 Alex Velenko New
[AArch64] NEON vdup testcases 0 0 0 2014-01-16 Alex Velenko New
[AArch64] Negate and set flags in shift mode 0 0 0 2013-04-10 Hurugalawadi, Naveen New
[AArch64] Negate with Compare instruction 0 0 0 2013-04-22 Hurugalawadi, Naveen New
[AArch64] Negate with Compare instruction 0 0 0 2013-04-19 Hurugalawadi, Naveen New
[AArch64] Obvious - Fix return types for vaddvq_<su>64 0 0 0 2013-09-04 James Greenhalgh New
[AArch64] One-liner: fix type of an add in SIMD registers 0 0 0 2014-08-20 Alan Lawrence New
[AArch64] Optimise comparison where intermediate result not used 0 0 0 2012-11-06 Ian Bolton New
[AArch64] Optimized implementation of vget_low_* in arm_neon.h. 0 0 0 2013-08-20 Tejas Belagod New
[AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant lane number 0 0 0 2014-09-05 Kyrylo Tkachov New
[AArch64] PR 63521. define REG_ALLOC_ORDER/HONOR_REG_ALLOC_ORDER 0 0 0 2015-05-20 Jiong Wang New
[AArch64] PR 64448: Combine ((x ^ y) & m) ^ x into bsl/bif instruction 0 0 0 2015-01-16 Kyrylo Tkachov New
[AArch64] PR target 66049: fix add/extend gcc test suite failures 0 0 0 2015-05-19 venkataramanan.kumar@amd.com New
[AArch64] PR target/66200 - gcc / libstdc++ TLC for weak memory models. 0 0 0 2015-05-21 Ramana Radhakrishnan New
[AArch64] PR target/66200 - gcc / libstdc++ TLC for weak memory models. 0 0 0 2015-05-20 Ramana Radhakrishnan New
[AArch64] PR target/66731 Fix fnmul insn with -frounding-math 0 0 0 2015-07-16 Szabolcs Nagy New
[AArch64] PR target/66731 Fix fnmul insn with -frounding-math 0 0 0 2015-07-09 Szabolcs Nagy New
[AArch64] PR target/66731 Fix fnmul insn with -frounding-math 0 0 0 2015-07-06 Szabolcs Nagy New
[AArch64] PR/64134: Make aarch64_expand_vector_init use 'ins' more often 0 0 0 2015-04-17 Alan Lawrence New
[AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics 0 0 0 2015-06-08 Alan Lawrence New
[AArch64] Peepholes to generate ldp and stp instructions 0 0 0 2013-03-26 Hurugalawadi, Naveen New
[AArch64] Prefer dup to zip for vec_perm_const; enable dup for bigendian; add testcase. 0 0 0 2014-08-04 Alan Lawrence New
[AArch64] Prevent generic pipeline description from dominating other pipeline descriptions. 0 0 0 2013-09-10 James Greenhalgh New
[AArch64] Properly cost MNEG/[SU]MNEGL patterns 0 0 0 2015-04-20 Kyrylo Tkachov New
[AArch64] Properly cost sign_extend+ashiftrt version of sbfx 0 0 0 2015-05-01 Kyrylo Tkachov New
[AArch64] Properly guard CUMULATIVE_ARGS definition and remove 'enum' from machine_mode in aarch64.h 0 0 0 2014-10-31 Kyrylo Tkachov New
[AArch64] Properly handle SHIFT ops and EXTEND in aarch64_rtx_mult_cost 0 0 0 2015-04-20 Kyrylo Tkachov New
[AArch64] Properly handle simple arith+extend ops in rtx costs 0 0 0 2015-07-28 Kyrylo Tkachov New
[AArch64] RFA: Use new rtl iterators in arm_cannot_copy_insn 0 0 0 2014-11-05 Richard Sandiford New
[AArch64] Re-organize aarch64_classify_symbol 0 0 0 2013-05-30 Marcus Shawcroft New
[AArch64] Refactor Advanced SIMD builtin initialisation. 0 0 0 2012-11-12 James Greenhalgh New
[AArch64] Refactor Advanced SIMD builtin initialisation. 0 0 0 2012-10-05 James Greenhalgh New
[AArch64] Refactor aarch64_mov_operand predicate. 0 0 0 2013-05-23 Marcus Shawcroft New
[AArch64] Refactor acquire/release determination into output template 0 0 0 2014-06-04 Jones, Joel New
[AArch64] Refactor reduc_<su>plus patterns. 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Refactor thunks code generation 0 0 0 2012-11-16 James Greenhalgh New
[AArch64] Refactor vector max and min RTL and builtins. 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Relax CANNOT_CHANGE_MODE_CLASS. 0 0 0 2014-01-16 Tejas Belagod New
[AArch64] Relax CANNOT_CHANGE_MODE_CLASS. 0 0 0 2013-11-28 Tejas Belagod New
[AArch64] Relax modes_tieable_p and cannot_change_mode_class 0 0 0 2014-02-18 James Greenhalgh New