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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[AArch64] Support BFI instruction and insv standard pattern
- - - -
-
-
-
2013-05-08
Ian Bolton
New
[AArch64] Support BFXIL in the backend
- - - -
-
-
-
2013-06-27
Ian Bolton
New
[AArch64] Support BICS instruction in the backend
- - - -
-
-
-
2013-05-01
Ian Bolton
New
[AArch64] Support BICS instruction in the backend
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Support EXTR in backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support LDR/STR to/from S and D registers
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Support NEG in vector registers for DI and SI mode
- - - -
-
-
-
2013-07-23
Ian Bolton
New
[AArch64] Support ROR in backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support SADDL/SSUBL/UADDL/USUBL
- - - -
-
-
-
2013-09-30
Vidya Praveen
New
[AArch64] Support SBC in the backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR)
- - - -
-
-
-
2013-08-20
Vidya Praveen
New
[AArch64] Support SISD variants of SCVTF,UCVTF
- - - -
-
-
-
2014-01-13
Vidya Praveen
New
[AArch64] Support abs standard pattern for DI mode
- - - -
-
-
-
2013-06-25
Ian Bolton
New
[AArch64] Support float->int conversions in vector registers.
- - - -
-
-
-
2013-05-01
James Greenhalgh
New
[AArch64] Support for CLZ
- - - -
-
-
-
2013-05-22
Vidya Praveen
New
[AArch64] Support for LDP/STP of Q-registers
[AArch64] Support for LDP/STP of Q-registers
- - - -
-
-
-
2018-06-04
Kyrill Tkachov
New
[AArch64] Support for SMLAL/SMLSL/UMLAL/UMLSL
- - - -
-
-
-
2013-06-14
Vidya Praveen
New
[AArch64] Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.
- - - -
-
-
-
2016-06-08
Bin Cheng
New
[AArch64] Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.
- - - -
-
-
-
2016-05-17
Bin Cheng
New
[AArch64] Support scalar form of FABD
- - - -
-
-
-
2013-05-02
Vidya Praveen
New
[AArch64] Support vrecp<esx> neon intrinsics in RTL.
- - - -
-
-
-
2013-04-22
James Greenhalgh
New
[AArch64] Support zero-extended move to FP register
[AArch64] Support zero-extended move to FP register
- - - -
-
-
-
2018-09-27
Wilco Dijkstra
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-09
Ramana Radhakrishnan
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-04
Ramana Radhakrishnan
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-03
Ramana Radhakrishnan
New
[AArch64] Sync merge libffi - fix call frame information in ffi_closure_SYSV
- - - -
-
-
-
2014-02-28
Yufeng Zhang
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-02-18
Alex Velenko
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-01-27
Alex Velenko
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-01-21
Alex Velenko
New
[AArch64] Testcases for ANDS instruction
- - - -
-
-
-
2013-05-01
Ian Bolton
New
[AArch64] Testcases for ANDS instruction
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Testcases for TST instruction
- - - -
-
-
-
2013-05-02
Ian Bolton
New
[AArch64] Tidy up aarch64_simd_expand_args
- - - -
-
-
-
2014-11-17
Alan Lawrence
New
[AArch64] Tidy: remove unused qualifier_const_pointer
- - - -
-
-
-
2014-08-20
Alan Lawrence
New
[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled
- - - -
-
-
-
2016-05-27
Kyrill Tkachov
New
[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled
- - - -
-
-
-
2016-05-20
Kyrill Tkachov
New
[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)
[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)
- - - -
-
-
-
2018-01-26
Richard Sandiford
New
[AArch64] Tighten address register subreg checks
- - - -
-
-
-
2017-08-22
Richard Sandiford
New
[AArch64] Tighten direct call pattern to repair -fno-plt
- - - -
-
-
-
2015-07-16
Jiong Wang
New
[AArch64] Tighten move constraints for symbolic operands
- - - -
-
-
-
2017-03-31
Richard Sandiford
New
[AArch64] Tighten predicate for CMP pattern.
- - - -
-
-
-
2012-09-26
Marcus Shawcroft
New
[AArch64] Tighten predicate for CMP pattern.
- - - -
-
-
-
2012-09-10
Tejas Belagod
New
[AArch64] Tighten predicates on SIMD shift intrinsics
- - - -
-
-
-
2014-09-25
James Greenhalgh
New
[AArch64] Tighten predicates on SIMD shift intrinsics
- - - -
-
-
-
2014-09-11
James Greenhalgh
New
[AArch64] Turn on -fasynchronous-unwind-tables and -funwind-tables by default.
[AArch64] Turn on -fasynchronous-unwind-tables and -funwind-tables by default.
- - - -
-
-
-
2018-03-13
Ramana Radhakrishnan
New
[AArch64] Turn on frame pointer / partial fix for PR84521
[AArch64] Turn on frame pointer / partial fix for PR84521
- - - -
-
-
-
2018-02-23
Ramana Radhakrishnan
New
[AArch64] Tweak Cortex-A57 vector cost
- - - -
-
-
-
2016-11-10
Wilco Dijkstra
New
[AArch64] Tweak aarch64_classify_address interface
- - 1 -
-
-
-
2017-08-22
Richard Sandiford
New
[AArch64] Tweak handling of fp moves via int registers
[AArch64] Tweak handling of fp moves via int registers
- - - -
-
-
-
2019-08-07
Richard Sandiford
New
[AArch64] Unify vec_set patterns, support floating-point vector modes properly
[AArch64] Unify vec_set patterns, support floating-point vector modes properly
- - - -
-
-
-
2018-05-15
Kyrill Tkachov
New
[AArch64] Update L2 cache size on Falkor's prefetch tuning structure.
[AArch64] Update L2 cache size on Falkor's prefetch tuning structure.
- - - -
-
-
-
2018-03-01
Luis Machado
New
[AArch64] Update alignment for -mcpu=generic
- - - -
-
-
-
2017-04-20
Wilco Dijkstra
New
[AArch64] Update alignment for -mcpu=generic
- - - -
-
-
-
2017-04-12
Wilco Dijkstra
New
[AArch64] Update comments on the usage of X30 in FIXED_REGISTERS and CALL_USED_REGISTERS
- - - -
-
-
-
2015-10-16
Jiong Wang
New
[AArch64] Update definitions of _FP_W_TYPE and _FP_WS_TYPE in libgcc to be based on 'long long'
- - - -
-
-
-
2013-04-18
Yufeng Zhang
New
[AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def
[AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def
- - - -
-
-
-
2019-09-10
Stamatis Markianos-Wright
New
[AArch64] Update insv_1.c test for Big Endian
- - - -
-
-
-
2013-06-24
Ian Bolton
New
[AArch64] Update patterns to support FP zero
- - - -
-
-
-
2015-10-08
Wilco
New
[AArch64] Update target testcases for gnu11
- - - -
-
-
-
2014-10-21
Jiong Wang
New
[AArch64] Updated stack-clash implementation supporting 64k probes. [patch (1/6)]
[AArch64] Updated stack-clash implementation supporting 64k probes. [patch (1/6)]
- - - -
-
-
-
2018-07-11
Tamar Christina
New
[AArch64] Upgrade integer MLA intrinsics to GCC vector extensions
[AArch64] Upgrade integer MLA intrinsics to GCC vector extensions
- - - -
-
-
-
2020-08-12
James Greenhalgh
New
[AArch64] Use "multiple" for type, where more than one instruction is used for a move
- - - -
-
-
-
2013-09-06
James Greenhalgh
New
[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions
- - - -
-
-
-
2017-03-16
Kyrill Tkachov
New
[AArch64] Use 128-bit vectors when autovectorizing 16-bit float types
- - - -
-
-
-
2017-01-23
James Greenhalgh
New
[AArch64] Use @ pattern to eliminate switch statement in one more place
[AArch64] Use @ pattern to eliminate switch statement in one more place
- - - -
-
-
-
2018-10-16
Kyrylo Tkachov
New
[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
- - - -
-
-
-
2014-09-02
Kyrylo Tkachov
New
[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
- - - -
-
-
-
2014-08-19
Kyrylo Tkachov
New
[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
- - - -
-
-
-
2014-08-19
Kyrylo Tkachov
New
[AArch64] Use CC_Z and CC_NZ with csinc and similar instructions
- - - -
-
-
-
2014-08-18
Kyrylo Tkachov
New
[AArch64] Use CSINC instead of CSEL to return 1
- - - -
-
-
-
2012-11-06
Ian Bolton
New
[AArch64] Use Cortex A53 rtx costs table in aarch64
- - - -
-
-
-
2013-11-25
Kyrylo Tkachov
New
[AArch64] Use Cortex-A57 rtx costs for the generic CPU
- - - -
-
-
-
2014-02-26
Kyrylo Tkachov
New
[AArch64] Use Enums for code models option selection
- - - -
-
-
-
2012-06-28
Tejas Belagod
New
[AArch64] Use GCC builtins to count leading/tailing zeros
- - - -
-
-
-
2014-01-07
Yufeng Zhang
New
[AArch64] Use LDP/STP in shrinkwrapping
[AArch64] Use LDP/STP in shrinkwrapping
- - - -
-
-
-
2018-01-05
Wilco Dijkstra
New
[AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- - - -
-
-
-
2014-08-13
Kyrylo Tkachov
New
[AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- - - -
-
-
-
2014-08-07
Kyrylo Tkachov
New
[AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- - - -
-
-
-
2014-08-07
Kyrylo Tkachov
New
[AArch64] Use MOVN to generate 64-bit negative immediates where sensible
- - - -
-
-
-
2014-05-08
Ian Bolton
New
[AArch64] Use Q-reg loads/stores in movmem expansion
[AArch64] Use Q-reg loads/stores in movmem expansion
- - - -
-
-
-
2018-12-21
Kyrill Tkachov
New
[AArch64] Use REG_P and CONST_INT_P instead of GET_CODE + comparison
- - - -
-
-
-
2014-08-05
Kyrylo Tkachov
New
[AArch64] Use SUBS for parallel subtraction and comparison with immediate
- - - -
-
-
-
2017-04-21
Kyrill Tkachov
New
[AArch64] Use __aarch64_vget_lane* macros for getting the lane in some lane multiply intrinsics
- - - -
-
-
-
2014-09-08
Kyrylo Tkachov
New
[AArch64] Use aarch64_fusion_enabled_p to check for insn fusion capabilities
- - - -
-
-
-
2016-05-27
Kyrill Tkachov
New
[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
- - - -
-
-
-
2017-11-06
Richard Sandiford
New
[AArch64] Use aarch64_sve_int_mode in SVE ACLE code
[AArch64] Use aarch64_sve_int_mode in SVE ACLE code
- - - -
-
-
-
2019-11-13
Richard Sandiford
New
[AArch64] Use aarch64_sync_memory_operand in atomic_store<mode> pattern
- - - -
-
-
-
2015-12-04
Bin Cheng
New
[AArch64] Use all SVE LD1RQ variants
[AArch64] Use all SVE LD1RQ variants
- - - -
-
-
-
2018-01-26
Richard Sandiford
New
[AArch64] Use arrays and loops rather than numbered variables in aarch64_operands_adjust_ok_for_ldp…
[AArch64] Use arrays and loops rather than numbered variables in aarch64_operands_adjust_ok_for_ldp…
- - - -
-
-
-
2018-07-10
Jackson Woodruff
New
[AArch64] Use calls for SVE TLSDEC
[AArch64] Use calls for SVE TLSDEC
- - - -
-
-
-
2019-09-25
Richard Sandiford
New
[AArch64] Use cinc for if_then_else of plus-immediates
- - - -
-
-
-
2015-07-16
Kyrylo Tkachov
New
[AArch64] Use cinc mnemonic for *csinc2<mode>_insn
- - - -
-
-
-
2015-07-15
Kyrylo Tkachov
New
[AArch64] Use common rtx cost table structures with arm
- - - -
-
-
-
2013-11-13
Kyrylo Tkachov
New
[AArch64] Use conditional negate for abs expansion
- - - -
-
-
-
2015-05-14
Wilco
New
[AArch64] Use conditional negate for abs expansion
- - - -
-
-
-
2015-03-03
Wilco
New
[AArch64] Use contains_mem_rtx_p to detect memory sub-rtxes
- - - -
-
-
-
2017-02-13
Kyrill Tkachov
New
[AArch64] Use default_elf_asm_named_section instead of special cased hook
- - - -
-
-
-
2016-06-22
Andreas Schwab
New
[AArch64] Use default_elf_asm_named_section instead of special cased hook
- - - -
-
-
-
2015-10-02
Ramana Radhakrishnan
New
[AArch64] Use extend_arith rtx cost appropriately
- - - -
-
-
-
2015-04-20
Kyrylo Tkachov
New
[AArch64] Use gen_frame_mem for callee-saves
- - - -
-
-
-
2017-08-04
Wilco Dijkstra
New
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