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«
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[AArch64] Separate shrink wrapping hooks implementation
- - - -
-
-
-
2016-11-11
Kyrill Tkachov
New
[AArch64] Separate shrink wrapping hooks implementation
- - - -
-
-
-
2016-11-10
Kyrill Tkachov
New
[AArch64] Set SLOW_BYTE_ACCESS
[AArch64] Set SLOW_BYTE_ACCESS
- - - -
-
-
-
2018-11-09
Wilco Dijkstra
New
[AArch64] Set SLOW_BYTE_ACCESS
[AArch64] Set SLOW_BYTE_ACCESS
- - - -
-
-
-
2017-11-17
Wilco Dijkstra
New
[AArch64] Set TARGET_OMIT_STRUCT_RETURN_REG to true.
- - - -
-
-
-
2016-04-26
Ramana Radhakrishnan
New
[AArch64] Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tree is the default node…
- - - -
-
-
-
2016-02-25
Kyrill Tkachov
New
[AArch64] Set default sched pressure algorithm
[AArch64] Set default sched pressure algorithm
- - 1 -
-
-
-
2017-11-02
Wilco Dijkstra
New
[AArch64] Set default values for stack-clash and do basic validation in back-end. [Patch (5/6)]
[AArch64] Set default values for stack-clash and do basic validation in back-end. [Patch (5/6)]
- - - -
-
-
-
2018-07-11
Tamar Christina
New
[AArch64] Set jump alignment to 4 for Cortex cores
- - - -
-
-
-
2017-04-20
Wilco Dijkstra
New
[AArch64] Set jump alignment to 4 for Cortex cores
- - - -
-
-
-
2017-04-12
Wilco Dijkstra
New
[AArch64] Set libgloss_dir for aarch64*-*-* targets
- - - -
-
-
-
2013-01-10
Yufeng Zhang
New
[AArch64] Shift right pattern fix
- - - -
-
-
-
2014-01-30
Alex Velenko
New
[AArch64] Simplify TLS pattern by hardcoding relocation modifiers into pattern
- - - -
-
-
-
2015-09-10
Jiong Wang
New
[AArch64] Simplify aarch64_can_eliminate
- - 1 -
-
-
-
2017-08-15
Wilco Dijkstra
New
[AArch64] Simplify aarch64_can_eliminate
- - - -
-
-
-
2017-08-07
Wilco Dijkstra
New
[AArch64] Simplify ashl<mode>3 expander for SHORT modes
- - - -
-
-
-
2016-04-27
Kyrill Tkachov
New
[AArch64] Simplify eh_return implementation
- - - -
-
-
-
2016-08-04
Wilco Dijkstra
New
[AArch64] Simplify frame layout for stack probing
- - - -
-
-
-
2017-08-15
Wilco Dijkstra
New
[AArch64] Simplify frame layout for stack probing
- - - -
-
-
-
2017-08-01
Wilco Dijkstra
New
[AArch64] Simplify frame layout for stack probing
- - - -
-
-
-
2017-07-25
Wilco Dijkstra
New
[AArch64] Simplify frame pointer logic
[AArch64] Simplify frame pointer logic
- - - -
-
-
-
2017-10-25
Wilco Dijkstra
New
[AArch64] Simplify movmem code by always doing overlapping copies when larger than 8 bytes.
[AArch64] Simplify movmem code by always doing overlapping copies when larger than 8 bytes.
- - - -
-
-
-
2018-06-19
Tamar Christina
New
[AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
- - - -
-
-
-
2016-05-17
James Greenhalgh
New
[AArch64] Simplify vreinterpret for float64x1_t using casts.
- - - -
-
-
-
2014-09-08
Alan Lawrence
New
[AArch64] Skip aarch64*-*-* for g++.dg/cpp0x/alias-decl-debug-0.C
- - - -
-
-
-
2013-05-28
Yufeng Zhang
New
[AArch64] Skip arm targets in vq*shr*n_high_n intrinsic tests
[AArch64] Skip arm targets in vq*shr*n_high_n intrinsic tests
- - - -
-
-
-
2020-11-09
David Candler
New
[AArch64] Skip gcc.target/aarch64/assembler_arch_1.c if assembler does not support it
- - - -
-
-
-
2016-02-16
Kyrill Tkachov
New
[AArch64] Some aarch64-builtins.c cleanup.
- - - -
-
-
-
2014-08-04
James Greenhalgh
New
[AArch64] Specify CRC and Crypto support for Cortex-A53, A57
- - - -
-
-
-
2014-01-16
Kyrylo Tkachov
New
[AArch64] Specify fp16 support for Cortex-A55 and Cortex-A75
[AArch64] Specify fp16 support for Cortex-A55 and Cortex-A75
- - - -
-
-
-
2017-12-11
Kyrill Tkachov
New
[AArch64] Split X-reg UBFIZ into W-reg LSL when possible
- - - -
-
-
-
2016-12-16
Kyrill Tkachov
New
[AArch64] Split X-reg UBFIZ into W-reg LSL when possible
- - - -
-
-
-
2016-12-08
Kyrill Tkachov
New
[AArch64] Split X-reg UBFX into W-reg LSR when possible
- - - -
-
-
-
2016-12-16
Kyrill Tkachov
New
[AArch64] Split X-reg UBFX into W-reg LSR when possible
- - - -
-
-
-
2016-12-08
Kyrill Tkachov
New
[AArch64] Split a move of Q-reg vectors contained in general regs.
- - - -
-
-
-
2012-09-10
Tejas Belagod
New
[AArch64] Split built-in function codes into major and minor codes
[AArch64] Split built-in function codes into major and minor codes
- - - -
-
-
-
2019-08-07
Richard Sandiford
New
[AArch64] Stop generating BSL for simple integer code
- - - -
-
-
-
2017-07-27
James Greenhalgh
New
[AArch64] Stop generating BSL for simple integer code
- - - -
-
-
-
2017-06-12
James Greenhalgh
New
[AArch64] Stop generating BSL for simple integer code
- - - -
-
-
-
2017-06-12
James Greenhalgh
New
[AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
[AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
- - - -
-
-
-
2019-09-10
Richard Sandiford
New
[AArch64] Support --mcmodel=tiny.
- - - -
-
-
-
2013-05-29
Marcus Shawcroft
New
[AArch64] Support AdvSIMD MOVI / MVNI shifting ones variant.
- - - -
-
-
-
2013-07-12
Tejas Belagod
New
[AArch64] Support BFI instruction and insv standard pattern
- - - -
-
-
-
2013-05-30
Ian Bolton
New
[AArch64] Support BFI instruction and insv standard pattern
- - - -
-
-
-
2013-05-20
Ian Bolton
New
[AArch64] Support BFI instruction and insv standard pattern
- - - -
-
-
-
2013-05-08
Ian Bolton
New
[AArch64] Support BFXIL in the backend
- - - -
-
-
-
2013-06-27
Ian Bolton
New
[AArch64] Support BICS instruction in the backend
- - - -
-
-
-
2013-05-01
Ian Bolton
New
[AArch64] Support BICS instruction in the backend
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Support EXTR in backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support LDR/STR to/from S and D registers
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Support NEG in vector registers for DI and SI mode
- - - -
-
-
-
2013-07-23
Ian Bolton
New
[AArch64] Support ROR in backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support SADDL/SSUBL/UADDL/USUBL
- - - -
-
-
-
2013-09-30
Vidya Praveen
New
[AArch64] Support SBC in the backend
- - - -
-
-
-
2013-03-14
Ian Bolton
New
[AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR)
- - - -
-
-
-
2013-08-20
Vidya Praveen
New
[AArch64] Support SISD variants of SCVTF,UCVTF
- - - -
-
-
-
2014-01-13
Vidya Praveen
New
[AArch64] Support abs standard pattern for DI mode
- - - -
-
-
-
2013-06-25
Ian Bolton
New
[AArch64] Support float->int conversions in vector registers.
- - - -
-
-
-
2013-05-01
James Greenhalgh
New
[AArch64] Support for CLZ
- - - -
-
-
-
2013-05-22
Vidya Praveen
New
[AArch64] Support for LDP/STP of Q-registers
[AArch64] Support for LDP/STP of Q-registers
- - - -
-
-
-
2018-06-04
Kyrill Tkachov
New
[AArch64] Support for SMLAL/SMLSL/UMLAL/UMLSL
- - - -
-
-
-
2013-06-14
Vidya Praveen
New
[AArch64] Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.
- - - -
-
-
-
2016-06-08
Bin Cheng
New
[AArch64] Support missing vcond pattern by adding/using vec_cmp/vcond_mask patterns.
- - - -
-
-
-
2016-05-17
Bin Cheng
New
[AArch64] Support scalar form of FABD
- - - -
-
-
-
2013-05-02
Vidya Praveen
New
[AArch64] Support vrecp<esx> neon intrinsics in RTL.
- - - -
-
-
-
2013-04-22
James Greenhalgh
New
[AArch64] Support zero-extended move to FP register
[AArch64] Support zero-extended move to FP register
- - - -
-
-
-
2018-09-27
Wilco Dijkstra
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-09
Ramana Radhakrishnan
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-04
Ramana Radhakrishnan
New
[AArch64] Switch constant pools to separate rodata sections.
- - - -
-
-
-
2015-11-03
Ramana Radhakrishnan
New
[AArch64] Sync merge libffi - fix call frame information in ffi_closure_SYSV
- - - -
-
-
-
2014-02-28
Yufeng Zhang
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-02-18
Alex Velenko
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-01-27
Alex Velenko
New
[AArch64] Testcase fix for __ATOMIC_CONSUME
- - - -
-
-
-
2015-01-21
Alex Velenko
New
[AArch64] Testcases for ANDS instruction
- - - -
-
-
-
2013-05-01
Ian Bolton
New
[AArch64] Testcases for ANDS instruction
- - - -
-
-
-
2013-04-26
Ian Bolton
New
[AArch64] Testcases for TST instruction
- - - -
-
-
-
2013-05-02
Ian Bolton
New
[AArch64] Tidy up aarch64_simd_expand_args
- - - -
-
-
-
2014-11-17
Alan Lawrence
New
[AArch64] Tidy: remove unused qualifier_const_pointer
- - - -
-
-
-
2014-08-20
Alan Lawrence
New
[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled
- - - -
-
-
-
2016-05-27
Kyrill Tkachov
New
[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion is enabled
- - - -
-
-
-
2016-05-20
Kyrill Tkachov
New
[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)
[AArch64] Tighten aarch64_secondary_reload condition (PR 83845)
- - - -
-
-
-
2018-01-26
Richard Sandiford
New
[AArch64] Tighten address register subreg checks
- - - -
-
-
-
2017-08-22
Richard Sandiford
New
[AArch64] Tighten direct call pattern to repair -fno-plt
- - - -
-
-
-
2015-07-16
Jiong Wang
New
[AArch64] Tighten move constraints for symbolic operands
- - - -
-
-
-
2017-03-31
Richard Sandiford
New
[AArch64] Tighten predicate for CMP pattern.
- - - -
-
-
-
2012-09-26
Marcus Shawcroft
New
[AArch64] Tighten predicate for CMP pattern.
- - - -
-
-
-
2012-09-10
Tejas Belagod
New
[AArch64] Tighten predicates on SIMD shift intrinsics
- - - -
-
-
-
2014-09-25
James Greenhalgh
New
[AArch64] Tighten predicates on SIMD shift intrinsics
- - - -
-
-
-
2014-09-11
James Greenhalgh
New
[AArch64] Turn on -fasynchronous-unwind-tables and -funwind-tables by default.
[AArch64] Turn on -fasynchronous-unwind-tables and -funwind-tables by default.
- - - -
-
-
-
2018-03-13
Ramana Radhakrishnan
New
[AArch64] Turn on frame pointer / partial fix for PR84521
[AArch64] Turn on frame pointer / partial fix for PR84521
- - - -
-
-
-
2018-02-23
Ramana Radhakrishnan
New
[AArch64] Tweak Cortex-A57 vector cost
- - - -
-
-
-
2016-11-10
Wilco Dijkstra
New
[AArch64] Tweak aarch64_classify_address interface
- - 1 -
-
-
-
2017-08-22
Richard Sandiford
New
[AArch64] Tweak handling of fp moves via int registers
[AArch64] Tweak handling of fp moves via int registers
- - - -
-
-
-
2019-08-07
Richard Sandiford
New
[AArch64] Unify vec_set patterns, support floating-point vector modes properly
[AArch64] Unify vec_set patterns, support floating-point vector modes properly
- - - -
-
-
-
2018-05-15
Kyrill Tkachov
New
[AArch64] Update L2 cache size on Falkor's prefetch tuning structure.
[AArch64] Update L2 cache size on Falkor's prefetch tuning structure.
- - - -
-
-
-
2018-03-01
Luis Machado
New
[AArch64] Update alignment for -mcpu=generic
- - - -
-
-
-
2017-04-20
Wilco Dijkstra
New
[AArch64] Update alignment for -mcpu=generic
- - - -
-
-
-
2017-04-12
Wilco Dijkstra
New
[AArch64] Update comments on the usage of X30 in FIXED_REGISTERS and CALL_USED_REGISTERS
- - - -
-
-
-
2015-10-16
Jiong Wang
New
[AArch64] Update definitions of _FP_W_TYPE and _FP_WS_TYPE in libgcc to be based on 'long long'
- - - -
-
-
-
2013-04-18
Yufeng Zhang
New
[AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def
[AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def
- - - -
-
-
-
2019-09-10
Stamatis Markianos-Wright
New
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