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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL PASS[PR110560]
RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL PASS[PR110560]
- - - -
-
-
-
2023-07-07
Li Xu
New
Extend streamer_mode_table size to MACHINE_MODE_BITSIZE.
Extend streamer_mode_table size to MACHINE_MODE_BITSIZE.
- - - -
-
-
-
2023-06-27
Li Xu
New
[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
- - - -
-
-
-
2023-06-25
Li Xu
New
RISC-V: force arg and target to reg rtx under -O0
RISC-V: force arg and target to reg rtx under -O0
- - - -
-
-
-
2023-06-25
Li Xu
New
[v2] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
[v2] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
- - - -
-
-
-
2023-06-20
Li Xu
New
RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
- - - -
-
-
-
2023-06-20
Li Xu
New
[v2] RISC-V: Fix VWEXTF iterator requirement
[v2] RISC-V: Fix VWEXTF iterator requirement
- - - -
-
-
-
2023-06-19
Li Xu
New
RISC-V: Fix iterator requirement
RISC-V: Fix iterator requirement
- - - -
-
-
-
2023-06-19
Li Xu
New
RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
- - - -
-
-
-
2023-06-05
Li Xu
New
[V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1])…
[V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1])…
- - - -
-
-
-
2023-05-10
Li Xu
New
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -…
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -…
- - - -
-
-
-
2023-05-10
Li Xu
New
RISC-V: Fix typo
RISC-V: Fix typo
- - - -
-
-
-
2023-04-04
Li Xu
New
RISC-V: Fix typo
RISC-V: Fix typo
- - - -
-
-
-
2023-04-03
Li Xu
New
[v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
[v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
- - - -
-
-
-
2024-03-18
Li, Pan2
New
[v1] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]
[v1] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]
- - - -
-
-
-
2024-03-12
Li, Pan2
New
[v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
[v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
- - - -
-
-
-
2024-03-12
Li, Pan2
New
[v2] VECT: Fix ICE for vectorizable LD/ST when both len and store are enabled
[v2] VECT: Fix ICE for vectorizable LD/ST when both len and store are enabled
- - - -
-
-
-
2024-03-10
Li, Pan2
New
[v1] VECT: Bugfix ICE for vectorizable_store when both len and mask
[v1] VECT: Bugfix ICE for vectorizable_store when both len and mask
- - - -
-
-
-
2024-03-08
Li, Pan2
New
[v2] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
[v2] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
- - - -
-
-
-
2024-03-06
Li, Pan2
New
[v1] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
[v1] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV
- - - -
-
-
-
2024-03-06
Li, Pan2
New
[v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]
[v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]
- - - -
-
-
-
2024-03-05
Li, Pan2
New
[v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
[v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
- - - -
-
-
-
2024-03-01
Li, Pan2
New
[v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
[v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
- - - -
-
-
-
2024-02-28
Li, Pan2
New
[v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
[v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
- - - -
-
-
-
2024-02-28
Li, Pan2
New
[v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
[v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
- - - -
-
-
-
2024-02-28
Li, Pan2
New
[v2] DSE: Bugfix ICE after allow vector type in get_stored_val
[v2] DSE: Bugfix ICE after allow vector type in get_stored_val
- - - -
-
-
-
2024-02-26
Li, Pan2
New
[v1] RTL: Bugfix ICE after allow vector type in DSE
[v1] RTL: Bugfix ICE after allow vector type in DSE
- - - -
-
-
-
2024-02-26
Li, Pan2
New
[v2] Draft|Internal-fn: Introduce internal fn saturation US_PLUS
[v2] Draft|Internal-fn: Introduce internal fn saturation US_PLUS
- - - -
-
-
-
2024-02-24
Li, Pan2
New
[v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
[v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
- - - -
-
-
-
2024-02-23
Li, Pan2
New
[v1] RISC-V: Upgrade RVV intrinsic version to 0.12
[v1] RISC-V: Upgrade RVV intrinsic version to 0.12
- - - -
-
-
-
2024-02-21
Li, Pan2
New
[v1] Internal-fn: Add new internal function SAT_ADDU
[v1] Internal-fn: Add new internal function SAT_ADDU
- - - -
-
-
-
2024-02-17
Li, Pan2
New
[v1] RISC-V: Fix misspelled term args in error_at message
[v1] RISC-V: Fix misspelled term args in error_at message
- - - -
-
-
-
2024-02-10
Li, Pan2
New
[v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
[v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
- - - -
-
-
-
2024-02-07
Li, Pan2
New
[v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty args
[v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty args
- - - -
-
-
-
2024-02-06
Li, Pan2
New
[v1] RISC-V: Cleanup the comments for the psabi
[v1] RISC-V: Cleanup the comments for the psabi
- - - -
-
-
-
2024-01-31
Li, Pan2
New
[v2] RISC-V: Bugfix for vls mode aggregated in GPR calling convention
[v2] RISC-V: Bugfix for vls mode aggregated in GPR calling convention
- - - -
-
-
-
2024-01-30
Li, Pan2
New
[v1] RISC-V: Bugfix for vls integer mode calling convention
[v1] RISC-V: Bugfix for vls integer mode calling convention
- - - -
-
-
-
2024-01-24
Li, Pan2
New
[v1] RISC-V: Fix asm checks regression due to recent middle-end change
[v1] RISC-V: Fix asm checks regression due to recent middle-end change
- - - -
-
-
-
2024-01-17
Li, Pan2
New
[v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
[v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
- - - -
-
-
-
2024-01-12
Li, Pan2
New
[v5] LOOP-UNROLL: Leverage HAS_SIGNED_ZERO for var expansion
[v5] LOOP-UNROLL: Leverage HAS_SIGNED_ZERO for var expansion
- - - -
-
-
-
2024-01-11
Li, Pan2
New
[v4] LOOP-UNROLL: Leverage HAS_SIGNED_ZERO for var expansion
[v4] LOOP-UNROLL: Leverage HAS_SIGNED_ZERO for var expansion
- - - -
-
-
-
2024-01-11
Li, Pan2
New
[v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
[v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option
- - - -
-
-
-
2024-01-02
Li, Pan2
New
[v2] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
[v2] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
- - - -
-
-
-
2023-12-26
Li, Pan2
New
[v2] RISC-V: XFail the signbit-5 run test for RVV
[v2] RISC-V: XFail the signbit-5 run test for RVV
- - - -
-
-
-
2023-12-23
Li, Pan2
New
[v1] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
[v1] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
- - - -
-
-
-
2023-12-23
Li, Pan2
New
[v1] RISC-V: XFail the signbit-5 run test for RVV
[v1] RISC-V: XFail the signbit-5 run test for RVV
- - - -
-
-
-
2023-12-21
Li, Pan2
New
[v3] RISC-V: Bugfix for the const vector in single steps
[v3] RISC-V: Bugfix for the const vector in single steps
- - - -
-
-
-
2023-12-20
Li, Pan2
New
[v2] RISC-V: Bugfix for the const vector in single steps
[v2] RISC-V: Bugfix for the const vector in single steps
- - - -
-
-
-
2023-12-20
Li, Pan2
New
[v1] RISC-V: Bugfix for the const vector in single steps
[v1] RISC-V: Bugfix for the const vector in single steps
- - - -
-
-
-
2023-12-20
Li, Pan2
New
[v2] RISC-V: Bugfix for the RVV const vector
[v2] RISC-V: Bugfix for the RVV const vector
- - - -
-
-
-
2023-12-18
Li, Pan2
New
[v1] RISC-V: Bugfix for the RVV const vector
[v1] RISC-V: Bugfix for the RVV const vector
- - - -
-
-
-
2023-12-18
Li, Pan2
New
[v1] RISC-V: Fix POLY INT handle bug
[v1] RISC-V: Fix POLY INT handle bug
- - - -
-
-
-
2023-12-18
Li, Pan2
New
[v1] RISC-V: Refine test cases for both PR112929 and PR112988
[v1] RISC-V: Refine test cases for both PR112929 and PR112988
- - - -
-
-
-
2023-12-13
Li, Pan2
New
[v1] RISC-V: Disable RVV VCOMPRESS avl propagation
[v1] RISC-V: Disable RVV VCOMPRESS avl propagation
- - - -
-
-
-
2023-12-12
Li, Pan2
New
[v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
[v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
- - - -
-
-
-
2023-12-08
Li, Pan2
New
[v1] RISC-V: Add test case for bug PR112813
[v1] RISC-V: Add test case for bug PR112813
- - - -
-
-
-
2023-12-04
Li, Pan2
New
[v4] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
[v4] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
- - - -
-
-
-
2023-12-02
Li, Pan2
New
[v3] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
[v3] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
- - - -
-
-
-
2023-12-01
Li, Pan2
New
[v2] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
[v2] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
- - - -
-
-
-
2023-12-01
Li, Pan2
New
[v1] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
[v1] RISC-V: Bugfix for legitimize move when get vec mode in zve32f
- - - -
-
-
-
2023-11-30
Li, Pan2
New
[v1] RISC-V: Bugfix for ICE in block move when zve32f
[v1] RISC-V: Bugfix for ICE in block move when zve32f
- - - -
-
-
-
2023-11-29
Li, Pan2
New
[v2] RISC-V: Refine the mask generation for vec_init case 2
[v2] RISC-V: Refine the mask generation for vec_init case 2
- - - -
-
-
-
2023-11-15
Li, Pan2
New
[v1] RISC-V: Refine the mask generation for vec_init case 2
[v1] RISC-V: Refine the mask generation for vec_init case 2
- - - -
-
-
-
2023-11-15
Li, Pan2
New
[v4] DSE: Allow vector type for get_stored_val when read < store
[v4] DSE: Allow vector type for get_stored_val when read < store
- - - -
-
-
-
2023-11-13
Li, Pan2
New
[v1] RISC-V: Fix RVV dynamic frm tests failure
[v1] RISC-V: Fix RVV dynamic frm tests failure
- - - -
-
-
-
2023-11-13
Li, Pan2
New
[v1] RISC-V: Support FP l/ll round and rint HF mode autovec
[v1] RISC-V: Support FP l/ll round and rint HF mode autovec
- - - -
-
-
-
2023-11-12
Li, Pan2
New
[v3] DSE: Allow vector type for get_stored_val when read < store
[v3] DSE: Allow vector type for get_stored_val when read < store
- - - -
-
-
-
2023-11-12
Li, Pan2
New
[v1] RISC-V: Add HFmode for l/ll round and rint autovec
[v1] RISC-V: Add HFmode for l/ll round and rint autovec
- - - -
-
-
-
2023-11-10
Li, Pan2
New
[v1] RISC-V: Support vec_init for trailing same element
[v1] RISC-V: Support vec_init for trailing same element
- - - -
-
-
-
2023-11-10
Li, Pan2
New
[v1] Internal-fn: Add FLOATN support for l/ll round and rint [PR/112432]
[v1] Internal-fn: Add FLOATN support for l/ll round and rint [PR/112432]
- - - -
-
-
-
2023-11-09
Li, Pan2
New
[v1] RISC-V: Refine frm emit after bb end in succ edges
[v1] RISC-V: Refine frm emit after bb end in succ edges
- - - -
-
-
-
2023-11-09
Li, Pan2
New
[v2] DSE: Allow vector type for get_stored_val when read < store
[v2] DSE: Allow vector type for get_stored_val when read < store
- - - -
-
-
-
2023-11-09
Li, Pan2
New
[v1] ISC-V: Support FP floor to i/l/ll diff size autovec
[v1] ISC-V: Support FP floor to i/l/ll diff size autovec
- - - -
-
-
-
2023-11-07
Li, Pan2
New
[v1] RISC-V: Support FP ceil to i/l/ll diff size autovec
[v1] RISC-V: Support FP ceil to i/l/ll diff size autovec
- - - -
-
-
-
2023-11-07
Li, Pan2
New
[v1] RISC-V: Support FP round to i/l/ll diff size autovec
[v1] RISC-V: Support FP round to i/l/ll diff size autovec
- - - -
-
-
-
2023-11-06
Li, Pan2
New
[v1] RISC-V: Adjust FP rint round tests for RV32
[v1] RISC-V: Adjust FP rint round tests for RV32
- - - -
-
-
-
2023-11-06
Li, Pan2
New
[v1] RISC-V: Support FP rint to i/l/ll diff size autovec
[v1] RISC-V: Support FP rint to i/l/ll diff size autovec
- - - -
-
-
-
2023-11-05
Li, Pan2
New
[v1] RISC-V: Remove HF modes of FP to INT rounding autovec
[v1] RISC-V: Remove HF modes of FP to INT rounding autovec
- - - -
-
-
-
2023-11-04
Li, Pan2
New
[v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator
[v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator
- - - -
-
-
-
2023-11-03
Li, Pan2
New
[v1] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator
[v1] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator
- - - -
-
-
-
2023-11-02
Li, Pan2
New
[v1] EXPMED: Allow vector mode for DSE extract_low_bits [PR111720]
[v1] EXPMED: Allow vector mode for DSE extract_low_bits [PR111720]
- - - -
-
-
-
2023-11-02
Li, Pan2
New
[v4] VECT: Refine the type size restriction of call vectorizer
[v4] VECT: Refine the type size restriction of call vectorizer
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2023-10-31
Li, Pan2
New
[v3] VECT: Refine the type size restriction of call vectorizer
[v3] VECT: Refine the type size restriction of call vectorizer
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-
-
-
2023-10-30
Li, Pan2
New
[v1] RISC-V: Fix one range-loop-construct warning of avlprop
[v1] RISC-V: Fix one range-loop-construct warning of avlprop
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-
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2023-10-28
Li, Pan2
New
[v2] VECT: Remove the type size restriction of vectorizer
[v2] VECT: Remove the type size restriction of vectorizer
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-
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-
2023-10-26
Li, Pan2
New
[v1] RISC-V: Remove unnecessary asm check for vec cvt
[v1] RISC-V: Remove unnecessary asm check for vec cvt
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-
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2023-10-23
Li, Pan2
New
[v1] RISC-V: Bugfix for merging undef tmp register for trunc
[v1] RISC-V: Bugfix for merging undef tmp register for trunc
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-
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-
2023-10-23
Li, Pan2
New
[v1] RISC-V: Remove unnecessary asm check for binop constraint
[v1] RISC-V: Remove unnecessary asm check for binop constraint
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-
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2023-10-23
Li, Pan2
New
[v1] RISC-V: Remove unnecessary asm check for rounding autovec
[v1] RISC-V: Remove unnecessary asm check for rounding autovec
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-
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2023-10-23
Li, Pan2
New
[v1] RISC-V: Bugfix for merging undefined tmp register in math
[v1] RISC-V: Bugfix for merging undefined tmp register in math
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-
-
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2023-10-23
Li, Pan2
New
[v2] RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]
[v2] RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]
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2023-10-20
Li, Pan2
New
[v1] RISC-V: Support partial VLS mode when preference fixed-vlmax
[v1] RISC-V: Support partial VLS mode when preference fixed-vlmax
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2023-10-20
Li, Pan2
New
[v1] RISC-V: Remove the type size restriction of vectorizer
[v1] RISC-V: Remove the type size restriction of vectorizer
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-
-
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2023-10-18
Li, Pan2
New
[v1] RISC-V: Refine run test cases of math autovec
[v1] RISC-V: Refine run test cases of math autovec
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP llfloor auto vectorization
[v1] RISC-V: Add test for FP llfloor auto vectorization
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP ifloor auto vectorization
[v1] RISC-V: Add test for FP ifloor auto vectorization
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP iceil auto vectorization
[v1] RISC-V: Add test for FP iceil auto vectorization
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-
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP llceil auto vectorization
[v1] RISC-V: Add test for FP llceil auto vectorization
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-
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP llround auto vectorization
[v1] RISC-V: Add test for FP llround auto vectorization
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-
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2023-10-13
Li, Pan2
New
[v1] RISC-V: Add test for FP iroundf auto vectorization
[v1] RISC-V: Add test for FP iroundf auto vectorization
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-
-
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2023-10-13
Li, Pan2
New
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