Show patches with: State = Action Required       |    Archived = No       |   69530 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in C - - - 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Implement vset_lane intrinsics in C - - - 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Implement vsqrt_f64 intrinsic - - - 0 0 0 2014-11-27 Kyrylo Tkachov New
[AArch64] Implement vsqrt_f64 intrinsic - - - 0 0 0 2014-11-17 Kyrylo Tkachov New
[AArch64] Implement workaround for ARM Cortex-A53 erratum 835769 - - - 0 0 0 2014-10-10 Kyrylo Tkachov New
[AArch64] Implementent sync gen and atomic builtins. - - - 0 0 0 2012-11-16 James Greenhalgh New
[AArch64] Improve Cortex-A53 FP scheduler - - - 0 0 0 2017-06-12 Wilco Dijkstra New
[AArch64] Improve Cortex-A53 integer scheduler - - - 0 0 0 2016-07-05 Wilco Dijkstra New
[AArch64] Improve Cortex-A53 scheduling of int/fp transfers - - - 0 0 0 2017-01-10 Wilco Dijkstra New
[AArch64] Improve Cortex-A53 shift bypass - - - 0 0 0 2017-04-27 Wilco Dijkstra New
[AArch64] Improve HFA code generation - - - 0 0 0 2017-06-20 James Greenhalgh New
[AArch64] Improve LDP/STP generation that requires a base register [AArch64] Improve LDP/STP generation that requires a base register - - - 0 0 0 2017-09-14 Jackson Woodruff New
[AArch64] Improve Neon store of zero - - - 0 0 0 2017-08-16 Jackson Woodruff New
[AArch64] Improve Neon store of zero - - - 0 0 0 2017-08-10 Jackson Woodruff New
[AArch64] Improve SHA1 scheduling - - - 0 0 0 2016-12-06 Wilco Dijkstra New
[AArch64] Improve SHA1 scheduling - - - 0 0 0 2016-11-14 Wilco Dijkstra New
[AArch64] Improve SHA1 scheduling - - - 0 0 0 2016-11-02 Wilco Dijkstra New
[AArch64] Improve SHA1 scheduling - - - 0 0 0 2016-10-25 Wilco Dijkstra New
[AArch64] Improve SIMD concatenation with zeroes - - - 0 0 0 2015-10-02 James Greenhalgh New
[AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook - - - 0 0 0 2014-08-01 Jiong Wang New
[AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook - - - 0 0 0 2014-08-01 Jiong Wang New
[AArch64] Improve TI mode address offsets - - - 0 0 0 2016-12-06 Wilco Dijkstra New
[AArch64] Improve TI mode address offsets - - - 0 0 0 2016-11-11 Wilco Dijkstra New
[AArch64] Improve TI mode address offsets - - - 0 0 0 2016-11-10 Wilco Dijkstra New
[AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt - - - 0 0 0 2015-07-28 Jiong Wang New
[AArch64] Improve aarch64_case_values_threshold setting - - - 0 0 0 2016-05-16 Wilco Dijkstra New
[AArch64] Improve aarch64_case_values_threshold setting - - - 0 0 0 2016-04-22 Wilco Dijkstra New
[AArch64] Improve aarch64_legitimate_constant_p - - - 0 0 0 2017-08-15 Wilco Dijkstra New
[AArch64] Improve aarch64_legitimate_constant_p - - - 0 0 0 2017-08-01 Wilco Dijkstra New
[AArch64] Improve aarch64_legitimate_constant_p - - - 0 0 0 2017-07-21 Wilco Dijkstra New
[AArch64] Improve aarch64_legitimate_constant_p - - - 0 0 0 2017-07-14 Wilco Dijkstra New
[AArch64] Improve aarch64_legitimate_constant_p - - - 0 0 0 2017-07-07 Wilco Dijkstra New
[AArch64] Improve aarch64_modes_tieable_p - - - 0 0 0 2016-04-22 Wilco Dijkstra New
[AArch64] Improve add immediate expansion - - - 0 0 0 2015-09-25 Wilco New
[AArch64] Improve address cost for -mcpu=generic - - - 0 0 0 2017-04-20 Wilco Dijkstra New
[AArch64] Improve address cost for -mcpu=generic - - - 0 0 0 2017-04-12 Wilco Dijkstra New
[AArch64] Improve addressing of TI/TFmode - - - 0 0 0 2017-08-15 Wilco Dijkstra New
[AArch64] Improve addressing of TI/TFmode - - - 0 0 0 2017-08-01 Wilco Dijkstra New
[AArch64] Improve addressing of TI/TFmode - - - 0 0 0 2017-07-20 Wilco Dijkstra New
[AArch64] Improve arm_neon.h vml<as>_lane handling. - - - 0 0 0 2013-09-13 James Greenhalgh New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber - - - 0 0 0 2015-01-27 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber - - - 0 0 0 2015-01-19 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber - - - 0 0 0 2015-01-19 Jiong Wang New
[AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber - - - 0 0 0 2014-12-15 Jiong Wang New
[AArch64] Improve code generation for float16 vector code - - - 0 0 0 2015-09-07 Alan Lawrence New
[AArch64] Improve comparison with complex immediates followed by branch/cset - - - 0 0 0 2015-10-08 Kyrylo Tkachov New
[AArch64] Improve csinc/csneg/csinv opportunities on immediates - - - 0 0 0 2015-07-10 Kyrylo Tkachov New
[AArch64] Improve description of <F>CM instructions in RTL - - - 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Improve dup pattern - - - 0 0 0 2017-06-20 Wilco Dijkstra New
[AArch64] Improve float to int moves - - - 0 0 0 2017-04-26 Wilco Dijkstra New
[AArch64] Improve handling of constants destined for FP_REGS - - - 0 0 0 2013-09-04 Ian Bolton New
[AArch64] Improve legitimize_address - - - 0 0 0 2016-09-06 Wilco Dijkstra New
[AArch64] Improve spill code - swap order in shl pattern - - - 0 0 0 2015-04-27 Wilco New
[AArch64] Improve spill code - swap order in shr patterns - - - 0 0 0 2015-07-27 Wilco New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-10-18 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-10-17 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-09-21 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-09-06 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-08-23 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-08-10 Wilco Dijkstra New
[AArch64] Improve stack adjustment - - - 0 0 0 2016-08-04 Wilco Dijkstra New
[AArch64] Improve vst4_lane intrinsics - - - 0 0 0 2014-02-13 James Greenhalgh New
[AArch64] Increase code alignment - - - 0 0 0 2016-06-21 Wilco Dijkstra New
[AArch64] Increase code alignment - - - 0 0 0 2016-06-03 Wilco Dijkstra New
[AArch64] Increase static buffer size in aarch64_rewrite_selected_cpu - - - 0 0 0 2015-04-20 Kyrylo Tkachov New
[AArch64] Inline calls to lrint when possible - - - 0 0 0 2017-06-07 Tamar Christina New
[AArch64] Introduce emit_frame_chain - - - 0 0 0 2017-08-15 Wilco Dijkstra New
[AArch64] Introduce emit_frame_chain - - - 0 0 0 2017-08-04 Wilco Dijkstra New
[AArch64] LINK_SPEC changes for Cortex-A53 erratum 835769 workaround - - - 0 0 0 2014-10-22 Kyrylo Tkachov New
[AArch64] LR register not used in leaf functions - - - 0 0 0 2014-09-30 Jiong Wang New
[AArch64] LR register not used in leaf functions - - - 0 0 0 2014-09-22 Kugan Vivekanandarajah New
[AArch64] Logical vector shift right conformance - - - 0 0 0 2014-02-25 Alex Velenko New
[AArch64] Make -mcpu, -march and -mtune case-insensitive. - - - 0 0 0 2014-01-17 Alan Lawrence New
[AArch64] Make <su>mull<q> target tests more robust. - - - 0 0 0 2013-01-08 Tejas Belagod New
[AArch64] Make MOVK output operand 2 in hex - - - 0 0 0 2013-03-20 Ian Bolton New
[AArch64] Make aarch64_min_divisions_for_recip_mul configurable - - - 0 0 0 2015-05-01 Wilco New
[AArch64] Make aarch64_min_divisions_for_recip_mul configurable - - - 0 0 0 2015-03-03 Wilco New
[AArch64] Make argument of ld1 intrinsics const. - - - 0 0 0 2013-01-07 James Greenhalgh New
[AArch64] Make gentune.sh also generate "generic_sched" attribute - - - 0 0 0 2014-12-17 James Greenhalgh New
[AArch64] Make gentune.sh also generate "generic_sched" attribute - - - 0 0 0 2014-09-25 James Greenhalgh New
[AArch64] Make integer vabs intrinsics UNSPECs - - - 0 0 0 2015-01-28 James Greenhalgh New
[AArch64] Make omit-frame-pointer work correctly - - - 0 0 0 2013-03-28 Ian Bolton New
[AArch64] Make reduc_* operations bigendian-safe. - - - 0 0 0 2013-11-15 Tejas Belagod New
[AArch64] Make sure start callee-save offset for D registers aligned - - - 0 0 0 2014-06-05 Jiong Wang New
[AArch64] Make vabs<q>_f<32, 64> a tree/gimple intrinsic. - - - 0 0 0 2013-04-25 James Greenhalgh New
[AArch64] Make zero_extends explicit for common SImode patterns - - - 0 0 0 2012-12-14 Ian Bolton New
[AArch64] Make zero_extends explicit for common SImode patterns - - - 0 0 0 2012-12-13 Ian Bolton New
[AArch64] Make zero_extends explicit for some SImode patterns - - - 0 0 0 2013-01-15 Ian Bolton New
[AArch64] Map fcvt intrinsics to builtin name directly. - - - 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Map frint intrinsics to standard pattern names directly. - - - 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Map standard pattern names to NEON intrinsics directly. - - - 0 0 0 2013-04-22 James Greenhalgh New
[AArch64] Mark symbols as constant - - - 0 0 0 2017-06-20 Wilco Dijkstra New
[AArch64] Mark symbols as constant - - - 0 0 0 2017-06-19 Wilco Dijkstra New
[AArch64] Merge stores of D register values of different modes [AArch64] Merge stores of D register values of different modes - - - 0 0 0 2017-09-06 Jackson Woodruff New
[AArch64] Minor refactoring of aarch64_add_offset - - - 0 0 0 2013-06-25 Yufeng Zhang New
[AArch64] Minor refactoring of aarch64_force_temporary - - - 0 0 0 2013-06-25 Yufeng Zhang New
[AArch64] Model CSEL instruction in Cortex-A57 scheduling model - - - 0 0 0 2016-06-06 Kyrill Tkachov New
[AArch64] Model Cortex-A53 load forwarding - - - 0 0 0 2017-04-20 Wilco Dijkstra New
[AArch64] Model Cortex-A53 load forwarding - - - 0 0 0 2017-04-05 Wilco Dijkstra New
[AArch64] Move immediate into Advanced SIMD scalar. - - - 0 0 0 2012-09-10 Tejas Belagod New
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