Show patches with: State = Action Required       |    Archived = No       |   126596 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
RISC-V: Support poly move manipulation and selftests. RISC-V: Support poly move manipulation and selftests. - - - - --- 2022-09-15 钟居哲 New
RISC-V: Support scheduling for sifive p600 series RISC-V: Support scheduling for sifive p600 series - - - - --- 2024-01-31 Monk Chiang New
RISC-V: Support segment intrinsics RISC-V: Support segment intrinsics - - - - --- 2023-04-21 钟居哲 New
RISC-V: Support simplify (-1-x) for vector. RISC-V: Support simplify (-1-x) for vector. - - - - --- 2023-08-16 Li, Pan2 via Gcc-patches New
RISC-V: Support simplifying x/(-1) to neg for vector. RISC-V: Support simplifying x/(-1) to neg for vector. - - - - --- 2023-09-20 Wang, Yanzhang New
RISC-V: Support strided load/store RISC-V: Support strided load/store - - - - --- 2023-10-31 钟居哲 New
RISC-V: Support the ins "rol" with immediate operand RISC-V: Support the ins "rol" with immediate operand - - - - --- 2022-11-28 Feng Wang New
RISC-V: Support trailing vec_init optimization RISC-V: Support trailing vec_init optimization - - - - --- 2023-11-14 钟居哲 New
RISC-V: Support variable index in vec_extract. RISC-V: Support variable index in vec_extract. - - - - --- 2023-07-05 Robin Dapp New
RISC-V: Support vcreate intrinsics for non-tuple types RISC-V: Support vcreate intrinsics for non-tuple types - - - - --- 2023-11-02 Li Xu New
RISC-V: Support vfwmacc combine lowering RISC-V: Support vfwmacc combine lowering - - - - --- 2023-06-28 钟居哲 New
RISC-V: Support vfwmul.vv combine lowering RISC-V: Support vfwmul.vv combine lowering - - - - --- 2023-06-28 钟居哲 New
RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering - - - - --- 2023-06-28 钟居哲 New
RISC-V: Support vi variant for vec_cmp RISC-V: Support vi variant for vec_cmp - - - - --- 2024-01-18 钟居哲 New
RISC-V: Support vle.v/vse.v intrinsics RISC-V: Support vle.v/vse.v intrinsics - - - - --- 2022-12-23 钟居哲 New
RISC-V: Support vundefine intrinsics for tuple types RISC-V: Support vundefine intrinsics for tuple types - - - - --- 2023-11-01 Li Xu New
RISC-V: Support widening register overlap for vf4/vf8 RISC-V: Support widening register overlap for vf4/vf8 - - - - --- 2023-11-30 钟居哲 New
RISC-V: Suppress bogus warning for VLS types RISC-V: Suppress bogus warning for VLS types - - - - --- 2023-09-08 钟居哲 New
RISC-V: Suppress riscv-selftests.cc warning. RISC-V: Suppress riscv-selftests.cc warning. - - - - --- 2022-09-17 钟居哲 New
RISC-V: Switch RVV cost model to generic vector cost model RISC-V: Switch RVV cost model to generic vector cost model - - - - --- 2024-01-10 钟居哲 New
RISC-V: Synthesize power-of-two constants. RISC-V: Synthesize power-of-two constants. - - - - --- 2023-05-30 Robin Dapp New
RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx. RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx. - - - - --- 2024-01-11 Jin Ma New
RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. - - - - --- 2024-01-29 Jin Ma New
RISC-V: THead: Fix missing CFI directives for th.sdd in prologue. RISC-V: THead: Fix missing CFI directives for th.sdd in prologue. - - 1 1 --- 2023-10-04 瞿仙淼 New
RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL] RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL] - - - - --- 2024-01-05 钟居哲 New
RISC-V: Teach liveness estimation be aware of .vi variant RISC-V: Teach liveness estimation be aware of .vi variant - - - - --- 2024-01-04 钟居哲 New
RISC-V: The 'multilib-generator' enhancement. RISC-V: The 'multilib-generator' enhancement. - - - - --- 2021-09-27 Geng Qi New
RISC-V: The 'multilib-generator' enhancement. RISC-V: The 'multilib-generator' enhancement. - - - - --- 2021-01-18 Geng Qi New
RISC-V: The 'multilib-generator' enhancement. RISC-V: The 'multilib-generator' enhancement. - - - - --- 2021-01-18 Geng Qi New
RISC-V: Throw compilation error for unknown sub-extension or supervisor extension RISC-V: Throw compilation error for unknown sub-extension or supervisor extension - - - - --- 2023-07-12 Lehua Ding New
RISC-V: Tweak the wording for the sorry message RISC-V: Tweak the wording for the sorry message - - - - --- 2024-01-19 Kito Cheng New
RISC-V: Unescape chars in pr111566.f90 test RISC-V: Unescape chars in pr111566.f90 test - - - - --- 2023-10-03 Patrick O'Neill New
RISC-V: Unify indention in riscv.md - - - - --- 2017-05-04 Palmer Dabbelt New
RISC-V: Update RVV integer compare simplification comments RISC-V: Update RVV integer compare simplification comments - - - - --- 2023-05-08 Li, Pan2 via Gcc-patches New
RISC-V: Update crypto vector ISA info with latest spec RISC-V: Update crypto vector ISA info with latest spec - - - - --- 2023-11-30 Feng Wang New
RISC-V: Update multilib-generator to handle V RISC-V: Update multilib-generator to handle V - - - - --- 2023-04-13 Palmer Dabbelt New
RISC-V: Update test expectancies with recent scheduler change RISC-V: Update test expectancies with recent scheduler change - - - - --- 2024-02-23 Edwin Lu New
RISC-V: Update testcase. RISC-V: Update testcase. - - - - --- 2019-03-18 Kito Cheng New
RISC-V: Update testcases info with new implement info RISC-V: Update testcases info with new implement info - - - - --- 2022-01-19 Liao Shihua New
RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. - - - - --- 2022-12-20 钟居哲 New
RISC-V: Use .p2align for code-alignment RISC-V: Use .p2align for code-alignment - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. - - - - --- 2023-10-16 钟居哲 New
RISC-V: Use binvi to cover more immediates than with xori alone RISC-V: Use binvi to cover more immediates than with xori alone - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use bseti to cover more immediates than with ori alone RISC-V: Use bseti to cover more immediates than with ori alone - - - - --- 2022-11-10 Philipp Tomsich New
RISC-V: Use convert instructions instead of calling library functions RISC-V: Use convert instructions instead of calling library functions - - 1 - --- 2024-03-18 Jivan Hakobyan New
RISC-V: Use dominance analysis in global vsetvl elimination RISC-V: Use dominance analysis in global vsetvl elimination - - - - --- 2023-09-11 钟居哲 New
RISC-V: Use extension instructions instead of bitwise "and" RISC-V: Use extension instructions instead of bitwise "and" - - - - --- 2023-05-23 Jivan Hakobyan New
RISC-V: Use merge approach to optimize vector permutation RISC-V: Use merge approach to optimize vector permutation - - - - --- 2023-06-14 钟居哲 New
RISC-V: Use new linker emulations for glibc ABI. RISC-V: Use new linker emulations for glibc ABI. - - - - --- 2018-05-04 Jim Wilson New
RISC-V: Use riscv_subword_address for atomic_test_and_set RISC-V: Use riscv_subword_address for atomic_test_and_set - - - - --- 2023-11-01 Patrick O'Neill New
RISC-V: Use safe_grow_cleared for vector info [PR111469] RISC-V: Use safe_grow_cleared for vector info [PR111469] - - - - --- 2023-09-30 Patrick O'Neill New
RISC-V: Use stdint-gcc.h in rvv testsuite RISC-V: Use stdint-gcc.h in rvv testsuite - - 1 - --- 2023-11-07 Christoph Müllner New
RISC-V: Use stdint-gcc.h in rvv testsuite RISC-V: Use stdint-gcc.h in rvv testsuite - - - - --- 2023-09-26 Patrick O'Neill New
RISC-V: Use the X iterator for eh_set_lr_{si,di} RISC-V: Use the X iterator for eh_set_lr_{si,di} - - - - --- 2022-08-06 Palmer Dabbelt New
RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. - - - - --- 2024-03-06 Robin Dapp New
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x - - - - --- 2020-02-18 Kito Cheng New
RISC-V: Using merge approach to optimize repeating sequence in vec_init RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - - --- 2023-05-12 钟居哲 New
RISC-V: VECT: Remember to assert any_known_not_updated_vssa RISC-V: VECT: Remember to assert any_known_not_updated_vssa - - - - --- 2023-11-06 Maxim Blinov New
RISC-V: VLA preempts VLS on unknown NITERS loop RISC-V: VLA preempts VLS on unknown NITERS loop - - - - --- 2024-01-11 钟居哲 New
RISC-V: Vectorized str(n)cmp and strlen. RISC-V: Vectorized str(n)cmp and strlen. - - - - --- 2023-11-30 Robin Dapp New
RISC-V: When the TARGET_COMPUTE_MULTILIB hook is implemented, check the version of each extension. RISC-V: When the TARGET_COMPUTE_MULTILIB hook is implemented, check the version of each extension. - - - - --- 2023-02-22 Jin Ma New
RISC-V: XFAIL scan dump fails for autovec PR111311 RISC-V: XFAIL scan dump fails for autovec PR111311 - - - - --- 2023-12-07 Edwin Lu New
RISC-V: Zihintpause: add __builtin_riscv_pause RISC-V: Zihintpause: add __builtin_riscv_pause - - - - --- 2022-11-13 Philipp Tomsich New
RISC-V: Zihintpause: add __builtin_riscv_pause RISC-V: Zihintpause: add __builtin_riscv_pause - - - - --- 2021-01-06 Philipp Tomsich New
RISC-V: add TARGET_ZBKB to the condition of bswapsi2, bswapdi2 and rotr<mode>3 patterns RISC-V: add TARGET_ZBKB to the condition of bswapsi2, bswapdi2 and rotr<mode>3 patterns - - - - --- 2023-04-10 Lin Sinan New
RISC-V: add option -m(no-)autovec-segment RISC-V: add option -m(no-)autovec-segment - - - - --- 2024-02-26 钟居哲 New
RISC-V: add option -m(no-)autovec-segment RISC-V: add option -m(no-)autovec-segment - - - - --- 2024-02-26 Greg McGary New
RISC-V: add static-pie support RISC-V: add static-pie support - - - - --- 2023-10-07 Wang, Yanzhang New
RISC-V: align RISC-V software division with hardware specification in case of division by zero RISC-V: align RISC-V software division with hardware specification in case of division by zero - - - - --- 2020-05-29 MOSER Virginie New
RISC-V: allow bseti on SImode without sign-extension RISC-V: allow bseti on SImode without sign-extension - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: allow vx instruction use "zero" as scalar register. RISC-V: allow vx instruction use "zero" as scalar register. - - - - --- 2023-02-07 钟居哲 New
RISC-V: avoid splitting small constant in <or_optab>i<mode>_extrabit pattern RISC-V: avoid splitting small constant in <or_optab>i<mode>_extrabit pattern - - - - --- 2023-04-10 Lin Sinan New
RISC-V: avoid splitting small constants in bcrli_nottwobits patterns RISC-V: avoid splitting small constants in bcrli_nottwobits patterns - - - - --- 2023-04-20 Jivan Hakobyan New
RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: branch-(not)equals-zero compares against $zero RISC-V: branch-(not)equals-zero compares against $zero - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: convert the mulh with 0 to mov 0 to the reg. RISC-V: convert the mulh with 0 to mov 0 to the reg. - - - - --- 2023-06-21 Li, Pan2 via Gcc-patches New
RISC-V: costs: handle BSWAP RISC-V: costs: handle BSWAP - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] - - 1 - --- 2023-03-01 Vineet Gupta New
RISC-V: costs: support shift-and-add in strength-reduction RISC-V: costs: support shift-and-add in strength-reduction - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: decouple stack allocation for rv32e w/o save-restore. RISC-V: decouple stack allocation for rv32e w/o save-restore. - - - - --- 2023-04-21 Fei Gao New
RISC-V: define _REENTRANT with -pthread RISC-V: define _REENTRANT with -pthread - - - - --- 2018-02-12 Andreas Schwab New
RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - - - 1 --- 2023-10-31 Vineet Gupta New
RISC-V: fix a typo in riscv.h RISC-V: fix a typo in riscv.h - - - - --- 2020-09-14 Yeting Kuo New
RISC-V: fix build issue with gcc 4.9.x RISC-V: fix build issue with gcc 4.9.x - 1 - - --- 2023-05-02 Romain Naour New
RISC-V: fix scalar crypto pattern RISC-V: fix scalar crypto pattern - - 1 1 --- 2023-12-13 Liao Shihua New
RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] - - - - --- 2024-01-16 Vineet Gupta New
RISC-V: fix vsetvli pass testsuite failure [PR/112447] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - 2 - - --- 2023-11-15 Vineet Gupta New
RISC-V: force arg and target to reg rtx under -O0 RISC-V: force arg and target to reg rtx under -O0 - - - - --- 2023-06-25 Li Xu New
RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] - - - - --- 2023-05-18 Vineet Gupta New
RISC-V: improve codegen for repeating large constants [3] RISC-V: improve codegen for repeating large constants [3] - - - - --- 2023-06-30 Vineet Gupta New
RISC-V: jal cannot refer to a default visibility symbol for shared object. RISC-V: jal cannot refer to a default visibility symbol for shared object. - - - - --- 2021-11-29 Nelson Chu New
RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand - - - - --- 2022-09-02 Vineet Gupta New
RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". - - - - --- 2022-10-10 钟居哲 New
RISC-V: move struct vector_type_info from *.h to *.cc. RISC-V: move struct vector_type_info from *.h to *.cc. - - - - --- 2022-10-10 钟居哲 New
RISC-V: optim const DF +0.0 store to mem [PR/110748] RISC-V: optim const DF +0.0 store to mem [PR/110748] - - 1 - --- 2023-07-21 Vineet Gupta New
RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb - - - - --- 2022-11-08 Philipp Tomsich New
RISC-V: optimize stack manipulation in save-restore RISC-V: optimize stack manipulation in save-restore - - - - --- 2022-11-30 Fei Gao New
RISC-V: output Autovec params explicitly in --help ... RISC-V: output Autovec params explicitly in --help ... - - - - --- 2023-08-22 Vineet Gupta New
RISC-V: remove param riscv-vector-abi. [PR113538] RISC-V: remove param riscv-vector-abi. [PR113538] - - - - --- 2024-01-25 Wang, Yanzhang New
RISC-V: remove param riscv-vector-abi. [PR113538] RISC-V: remove param riscv-vector-abi. [PR113538] - - - - --- 2024-01-25 Wang, Yanzhang New
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