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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISC-V: Add avail interface into function_group_info
RISC-V: Add avail interface into function_group_info
- - - -
-
-
-
2023-12-07
Feng Wang
New
RISC-V: Add available vector size for RVV
RISC-V: Add available vector size for RVV
- - - -
-
-
-
2023-10-09
juzhe.zhong@rivai.ai
New
RISC-V: Add basic vec_init support for RVV auto-vectorizaiton
RISC-V: Add basic vec_init support for RVV auto-vectorizaiton
- - - -
-
-
-
2023-05-10
juzhe.zhong@rivai.ai
New
RISC-V: Add bext pattern for ZBS
RISC-V: Add bext pattern for ZBS
- - - -
-
-
-
2023-05-04
Raphael Moreira Zinsly
New
RISC-V: Add binary op vx constraint tests
RISC-V: Add binary op vx constraint tests
- - - -
-
-
-
2023-02-03
juzhe.zhong@rivai.ai
New
RISC-V: Add binary vx C/C++ support
RISC-V: Add binary vx C/C++ support
- - - -
-
-
-
2023-02-03
juzhe.zhong@rivai.ai
New
RISC-V: Add binop constraint tests
RISC-V: Add binop constraint tests
- - - -
-
-
-
2023-01-31
juzhe.zhong@rivai.ai
New
RISC-V: Add binop constraints tests for integer compare
RISC-V: Add binop constraints tests for integer compare
- - - -
-
-
-
2023-02-13
juzhe.zhong@rivai.ai
New
RISC-V: Add blocker for gather/scatter auto-vectorization
RISC-V: Add blocker for gather/scatter auto-vectorization
- - - -
-
-
-
2023-12-05
juzhe.zhong@rivai.ai
New
RISC-V: Add builtin .def file dependencies
RISC-V: Add builtin .def file dependencies
- - - -
-
-
-
2023-09-19
Tsukasa OI
New
RISC-V: Add check for types without insn reservations
RISC-V: Add check for types without insn reservations
- - - -
-
-
-
2023-11-01
Edwin Lu
New
RISC-V: Add combine optimization by slideup for vec_init vectorization
RISC-V: Add combine optimization by slideup for vec_init vectorization
- - - -
-
-
-
2023-11-10
juzhe.zhong@rivai.ai
New
RISC-V: Add comments of some functions
RISC-V: Add comments of some functions
- - - -
-
-
-
2023-06-13
juzhe.zhong@rivai.ai
New
RISC-V: Add conditional autovec convert(INT<->FP) patterns
RISC-V: Add conditional autovec convert(INT<->FP) patterns
- - - -
-
-
-
2023-08-24
Lehua Ding
New
RISC-V: Add conditional convert autovec patterns between FPs
RISC-V: Add conditional convert autovec patterns between FPs
- - - -
-
-
-
2023-08-23
Lehua Ding
New
RISC-V: Add conditional sign/zero extension and truncation autovec patterns
RISC-V: Add conditional sign/zero extension and truncation autovec patterns
- - - -
-
-
-
2023-08-23
Lehua Ding
New
RISC-V: Add conditional sqrt autovec pattern
RISC-V: Add conditional sqrt autovec pattern
- - - -
-
-
-
2023-09-04
Lehua Ding
New
RISC-V: Add conditional unary neg/abs/not autovec patterns
RISC-V: Add conditional unary neg/abs/not autovec patterns
- - - -
-
-
-
2023-08-22
Lehua Ding
New
RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings.
RISC-V: Add configure option: --with-multilib-config to flexible config multi-lib settings.
- - - -
-
-
-
2020-10-16
Kito Cheng
New
RISC-V: Add constraint tests
RISC-V: Add constraint tests
- - - -
-
-
-
2023-02-07
juzhe.zhong@rivai.ai
New
RISC-V: Add crypto machine descriptions
RISC-V: Add crypto machine descriptions
- - - -
-
-
-
2023-12-22
Feng Wang
New
RISC-V: Add csrr vlenb instruction.
RISC-V: Add csrr vlenb instruction.
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add custom RTEMS multilibs
RISC-V: Add custom RTEMS multilibs
- - - -
-
-
-
2018-06-14
Sebastian Huber
New
RISC-V: Add divmod instruction support
RISC-V: Add divmod instruction support
- - - -
-
-
-
2023-02-17
Matevos Mehrabyan
New
RISC-V: Add duplicate vector support.
RISC-V: Add duplicate vector support.
- - - -
-
-
-
2022-11-25
juzhe.zhong@rivai.ai
New
RISC-V: Add dynamic LMUL compile option
RISC-V: Add dynamic LMUL compile option
- - - -
-
-
-
2023-08-31
juzhe.zhong@rivai.ai
New
RISC-V: Add early continue for ENTRY and EXIT block
RISC-V: Add early continue for ENTRY and EXIT block
- - - -
-
-
-
2023-08-25
juzhe.zhong@rivai.ai
New
RISC-V: Add explicit braces to eliminate warning.
RISC-V: Add explicit braces to eliminate warning.
- - - -
-
-
-
2023-11-29
Li Xu
New
RISC-V: Add fault first load C/C++ support
RISC-V: Add fault first load C/C++ support
- - - -
-
-
-
2023-03-07
juzhe.zhong@rivai.ai
New
RISC-V: Add fixed PR111255 testcase by other patch
RISC-V: Add fixed PR111255 testcase by other patch
- - - -
-
-
-
2023-09-18
Lehua Ding
New
RISC-V: Add fixed-point support
RISC-V: Add fixed-point support
- - - -
-
-
-
2023-02-10
juzhe.zhong@rivai.ai
New
RISC-V: Add floating-point RVV C/C++ api
RISC-V: Add floating-point RVV C/C++ api
- - - -
-
-
-
2023-02-17
juzhe.zhong@rivai.ai
New
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support
- - - -
-
-
-
2023-05-29
juzhe.zhong@rivai.ai
New
RISC-V: Add function comment for cleanup_insns.
RISC-V: Add function comment for cleanup_insns.
- - - -
-
-
-
2023-04-23
juzhe.zhong@rivai.ai
New
RISC-V: Add h extension support
RISC-V: Add h extension support
- - - -
-
-
-
2022-10-24
Kito Cheng
New
RISC-V: Add has compatible check for conflict vsetvl fusion
RISC-V: Add has compatible check for conflict vsetvl fusion
- - - -
-
-
-
2024-01-17
juzhe.zhong@rivai.ai
New
RISC-V: Add implementation for builtin overflow
RISC-V: Add implementation for builtin overflow
- - - -
-
-
-
2021-01-21
Levy Hsu
New
RISC-V: Add indexed loads/stores C/C++ intrinsic support
RISC-V: Add indexed loads/stores C/C++ intrinsic support
- - - -
-
-
-
2023-01-29
juzhe.zhong@rivai.ai
New
RISC-V: Add indexed loads/stores constraints testcases
RISC-V: Add indexed loads/stores constraints testcases
- - - -
-
-
-
2023-01-29
juzhe.zhong@rivai.ai
New
RISC-V: Add initial cost handling for segment loads/stores.
RISC-V: Add initial cost handling for segment loads/stores.
- - - -
-
-
-
2024-02-26
Robin Dapp
New
RISC-V: Add initial pipeline description for an out-of-order core.
RISC-V: Add initial pipeline description for an out-of-order core.
- - - -
-
-
-
2023-08-23
Robin Dapp
New
RISC-V: Add integer binary vv C/C++ API support
RISC-V: Add integer binary vv C/C++ API support
- - - -
-
-
-
2023-01-31
juzhe.zhong@rivai.ai
New
RISC-V: Add integer compare C/C++ intrinsic support
RISC-V: Add integer compare C/C++ intrinsic support
- - - -
-
-
-
2023-02-13
juzhe.zhong@rivai.ai
New
RISC-V: Add integer widening instructions
RISC-V: Add integer widening instructions
- - - -
-
-
-
2023-02-07
juzhe.zhong@rivai.ai
New
RISC-V: Add interrupt attribute modes.
RISC-V: Add interrupt attribute modes.
- - - -
-
-
-
2018-06-06
Jim Wilson
New
RISC-V: Add interrupt attribute support.
RISC-V: Add interrupt attribute support.
- - - -
-
-
-
2018-05-25
Jim Wilson
New
RISC-V: Add local user vsetvl instruction elimination
RISC-V: Add local user vsetvl instruction elimination
- - - -
-
-
-
2023-04-07
juzhe.zhong@rivai.ai
New
RISC-V: Add macro for ilp32e ABI. Cleanup white space.
RISC-V: Add macro for ilp32e ABI. Cleanup white space.
- - - -
-
-
-
2018-10-03
Jim Wilson
New
RISC-V: Add minimal support for 7 new unprivileged extensions
RISC-V: Add minimal support for 7 new unprivileged extensions
- - - -
-
-
-
2024-02-01
Monk Chiang
New
RISC-V: Add missed cond autovec testcases
RISC-V: Add missed cond autovec testcases
- - - -
-
-
-
2023-09-12
Lehua Ding
New
RISC-V: Add missing modes to the iterators
RISC-V: Add missing modes to the iterators
- - - -
-
-
-
2023-08-10
juzhe.zhong@rivai.ai
New
RISC-V: Add missing negate patterns.
RISC-V: Add missing negate patterns.
- - - -
-
-
-
2018-09-26
Jim Wilson
New
RISC-V: Add missing torture-init and torture-finish for rvv.exp
RISC-V: Add missing torture-init and torture-finish for rvv.exp
- - - -
-
-
-
2023-05-22
Kito Cheng
New
RISC-V: Add missing vsetvl instruction type.
RISC-V: Add missing vsetvl instruction type.
- - - -
-
-
-
2022-10-10
juzhe.zhong@rivai.ai
New
RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions
RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions
- - - -
-
-
-
2023-05-17
juzhe.zhong@rivai.ai
New
RISC-V: Add more SLP tests
RISC-V: Add more SLP tests
- - - -
-
-
-
2023-06-13
juzhe.zhong@rivai.ai
New
RISC-V: Add naked function support.
RISC-V: Add naked function support.
- - - -
-
-
-
2018-01-10
Jim Wilson
New
RISC-V: Add new line at end of file.
RISC-V: Add new line at end of file.
- - - -
-
-
-
2022-10-12
juzhe.zhong@rivai.ai
New
RISC-V: Add new option -march=help to print all supported extensions
RISC-V: Add new option -march=help to print all supported extensions
- - 1 -
-
-
-
2024-02-15
Kito Cheng
New
RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]
RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]
- - - -
-
-
-
2023-09-26
juzhe.zhong@rivai.ai
New
RISC-V: Add patterns to convert AND mask to two shifts.
RISC-V: Add patterns to convert AND mask to two shifts.
- - - -
-
-
-
2018-06-30
Jim Wilson
New
RISC-V: Add permutation C/C++ support
RISC-V: Add permutation C/C++ support
- - - -
-
-
-
2023-02-27
juzhe.zhong@rivai.ai
New
RISC-V: Add popcount fallback expander.
RISC-V: Add popcount fallback expander.
- - - -
-
-
-
2023-10-18
Robin Dapp
New
RISC-V: Add probability model of each block to prevent endless loop of Phase 3
RISC-V: Add probability model of each block to prevent endless loop of Phase 3
- - - -
-
-
-
2023-01-09
juzhe.zhong@rivai.ai
New
RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations
RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations
- - - -
-
-
-
2023-06-01
juzhe.zhong@rivai.ai
New
RISC-V: Add rawmemchr expander.
RISC-V: Add rawmemchr expander.
- - - -
-
-
-
2023-10-26
Robin Dapp
New
RISC-V: Add regression test for vsetvl bug pr113429
RISC-V: Add regression test for vsetvl bug pr113429
- - - -
-
-
-
2024-01-24
Patrick O'Neill
New
RISC-V: Add require-effective-target to pr113429 testcase
RISC-V: Add require-effective-target to pr113429 testcase
- - - -
-
-
-
2024-01-27
Patrick O'Neill
New
RISC-V: Add required tls to read thread pointer test
RISC-V: Add required tls to read thread pointer test
- - - -
-
-
-
2023-04-27
Li, Pan2
New
RISC-V: Add required_extensions in function_group
RISC-V: Add required_extensions in function_group
- - - -
-
-
-
2023-12-18
Feng Wang
New
RISC-V: Add riscv-vsetvl.def to t-riscv
RISC-V: Add riscv-vsetvl.def to t-riscv
- - - -
-
-
-
2023-08-22
juzhe.zhong@rivai.ai
New
RISC-V: Add riscv_vector_cc function attribute
RISC-V: Add riscv_vector_cc function attribute
- - - -
-
-
-
2024-02-27
Li Xu
New
RISC-V: Add rotate immediate regression test
RISC-V: Add rotate immediate regression test
- - - -
-
-
-
2023-08-16
Patrick O'Neill
New
RISC-V: Add rounding mode enum for fixed-point intrinsics
RISC-V: Add rounding mode enum for fixed-point intrinsics
- - - -
-
-
-
2023-05-17
juzhe.zhong@rivai.ai
New
RISC-V: Add rounding mode operand for fixed-point patterns
RISC-V: Add rounding mode operand for fixed-point patterns
- - - -
-
-
-
2023-05-15
juzhe.zhong@rivai.ai
New
RISC-V: Add rounding mode operand for floating point instructions
RISC-V: Add rounding mode operand for floating point instructions
- - - -
-
-
-
2023-05-15
juzhe.zhong@rivai.ai
New
RISC-V: Add runtime invariant support
RISC-V: Add runtime invariant support
- - - -
-
-
-
2022-08-17
juzhe.zhong@rivai.ai
New
RISC-V: Add saturating Add && Sub vx constraint tests
RISC-V: Add saturating Add && Sub vx constraint tests
- - - -
-
-
-
2023-02-05
juzhe.zhong@rivai.ai
New
RISC-V: Add saturating Addition && Subtraction C/C++ Support
RISC-V: Add saturating Addition && Subtraction C/C++ Support
- - - -
-
-
-
2023-02-05
juzhe.zhong@rivai.ai
New
RISC-V: Add scalar move support and fix VSETVL bugs
RISC-V: Add scalar move support and fix VSETVL bugs
- - - -
-
-
-
2023-02-24
juzhe.zhong@rivai.ai
New
RISC-V: Add shift constraint tests
RISC-V: Add shift constraint tests
- - - -
-
-
-
2023-01-31
juzhe.zhong@rivai.ai
New
RISC-V: Add sifive-7 pipeline description.
RISC-V: Add sifive-7 pipeline description.
- - - -
-
-
-
2019-03-26
Jim Wilson
New
RISC-V: Add sign-extending variants for vmv.x.s.
RISC-V: Add sign-extending variants for vmv.x.s.
- - - -
-
-
-
2023-06-12
Robin Dapp
New
RISC-V: Add split pattern to generate SFB instructions. [PR113095]
RISC-V: Add split pattern to generate SFB instructions. [PR113095]
- - - -
-
-
-
2024-01-19
Monk Chiang
New
RISC-V: Add srl.vv C API tests
RISC-V: Add srl.vv C API tests
- - - -
-
-
-
2023-01-31
juzhe.zhong@rivai.ai
New
RISC-V: Add support for -mcpu option.
RISC-V: Add support for -mcpu option.
- - - -
-
-
-
2020-10-13
Kito Cheng
New
RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)
RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)
- - - -
-
-
-
2022-11-18
Christoph Müllner
New
RISC-V: Add support for B standard extension
RISC-V: Add support for B standard extension
- - - -
-
-
-
2024-02-06
Edwin Lu
New
RISC-V: Add support for riscv-*-*.
RISC-V: Add support for riscv-*-*.
- - - -
-
-
-
2018-07-06
Jim Wilson
New
RISC-V: Add target machine headers as a dependency for riscv-sr.o
RISC-V: Add target machine headers as a dependency for riscv-sr.o
- - - -
-
-
-
2022-01-31
Maciej W. Rozycki
New
RISC-V: Add ternary constraint tests
RISC-V: Add ternary constraint tests
- - - -
-
-
-
2023-02-14
juzhe.zhong@rivai.ai
New
RISC-V: Add test cases for the RVV mask insn shortcut.
RISC-V: Add test cases for the RVV mask insn shortcut.
- - - -
-
-
-
2023-04-14
Li, Pan2 via Gcc-patches
New
RISC-V: Add test for vfloat16*_t (non tuple) types
RISC-V: Add test for vfloat16*_t (non tuple) types
- - - -
-
-
-
2023-06-01
Li, Pan2 via Gcc-patches
New
RISC-V: Add testcase for PR114749.
RISC-V: Add testcase for PR114749.
- - - -
-
-
-
2024-04-25
Robin Dapp
New
RISC-V: Add testcase for VSETVL PASS
RISC-V: Add testcase for VSETVL PASS
- - - -
-
-
-
2023-02-24
juzhe.zhong@rivai.ai
New
RISC-V: Add testcase for testing li pseudo instruction
RISC-V: Add testcase for testing li pseudo instruction
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2019-08-23
Kito Cheng
New
RISC-V: Add testcase for vrsub.vi auto-vectorization
RISC-V: Add testcase for vrsub.vi auto-vectorization
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2023-05-31
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for AVL=REG support
RISC-V: Add testcases for AVL=REG support
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2023-01-09
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for IMM (0 ~ 31) AVL
RISC-V: Add testcases for IMM (0 ~ 31) AVL
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2023-01-04
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for RVV auto-vectorization
RISC-V: Add testcases for RVV auto-vectorization
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2023-04-07
juzhe.zhong@rivai.ai
New
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