Show patches with: State = Action Required       |    Archived = No       |   127320 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v4,34/34] RISC-V: Add vsuxeix.C RISC-V: Add RVV (RISC-V 'V' Extension) support - - - - --- 2022-06-01 Juzhe-Zhong New
[1/1] Fix bit-position comparison middle-end: Fix bit position comparison - - - - --- 2022-07-27 Juzhe-Zhong New
RISC-V: Add runtime invariant support RISC-V: Add runtime invariant support - - - - --- 2022-08-17 Juzhe-Zhong New
middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with… middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with… - - - - --- 2022-08-18 Juzhe-Zhong New
middle-end: Fix issue of poly_uint16 (1, 1) in self test middle-end: Fix issue of poly_uint16 (1, 1) in self test - - - - --- 2022-08-22 Juzhe-Zhong New
middle-end: Fix unexpected warnings for RISC-V port. middle-end: Fix unexpected warnings for RISC-V port. - - - - --- 2022-08-23 Juzhe-Zhong New
RISC-V: Add vector registers and classification RISC-V: Add vector registers and classification - - - - --- 2022-08-26 Juzhe-Zhong New
RISC-V: Add RVV instructions classification RISC-V: Add RVV instructions classification - - - - --- 2022-08-27 Juzhe-Zhong New
RISC-V: Add RVV registers RISC-V: Add RVV registers - - - - --- 2022-08-27 Juzhe-Zhong New
RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN - - - - --- 2022-08-30 Juzhe-Zhong New
RISC-V: Fix annotation RISC-V: Fix annotation - - - - --- 2022-08-30 Juzhe-Zhong New
RISC-V: Add RVV constraints. RISC-V: Add RVV constraints. - - - - --- 2022-08-30 Juzhe-Zhong New
RISC-V: Add csrr vlenb instruction. RISC-V: Add csrr vlenb instruction. - - - - --- 2022-08-30 Juzhe-Zhong New
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE - - - - --- 2022-08-30 Juzhe-Zhong New
RISC-V: Support poly move manipulation and selftests. RISC-V: Support poly move manipulation and selftests. - - - - --- 2022-09-15 Juzhe-Zhong New
RISC-V: Add RVV machine modes. RISC-V: Add RVV machine modes. - - - - --- 2022-09-15 Juzhe-Zhong New
RISC-V: Add RVV machine modes. RISC-V: Add RVV machine modes. - - - - --- 2022-09-15 Juzhe-Zhong New
RISC-V: Suppress riscv-selftests.cc warning. RISC-V: Suppress riscv-selftests.cc warning. - - - - --- 2022-09-17 Juzhe-Zhong New
DSE: Enhance dse with def-ref analysis DSE: Enhance dse with def-ref analysis - - - - --- 2022-09-22 Juzhe-Zhong New
DSE: Enhance dse with def-ref analysis DSE: Enhance dse with def-ref analysis - - - - --- 2022-09-22 Juzhe-Zhong New
RISC-V: Add ABI-defined RVV types. RISC-V: Add ABI-defined RVV types. - - - - --- 2022-09-27 Juzhe-Zhong New
[Unfinished] Add first-order recurrence autovectorization [Unfinished] Add first-order recurrence autovectorization - - - - --- 2022-09-29 Juzhe-Zhong New
RISC-V: Introduce RVV header to enable builtin types RISC-V: Introduce RVV header to enable builtin types - - - - --- 2022-09-30 Juzhe-Zhong New
Add first-order recurrence autovectorization Add first-order recurrence autovectorization - - - - --- 2022-09-30 Juzhe-Zhong New
RISC-V: Add missing vsetvl instruction type. RISC-V: Add missing vsetvl instruction type. - - - - --- 2022-10-10 Juzhe-Zhong New
RISC-V: move struct vector_type_info from *.h to *.cc. RISC-V: move struct vector_type_info from *.h to *.cc. - - - - --- 2022-10-10 Juzhe-Zhong New
RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name". - - - - --- 2022-10-10 Juzhe-Zhong New
RISC-V: Move function place to make it looks better. RISC-V: Move function place to make it looks better. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Refine register_builtin_types function. RISC-V: Refine register_builtin_types function. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Clang-format add_vector_attribute function. RISC-V: Clang-format add_vector_attribute function. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Remove TUPLE size macro define. RISC-V: Remove TUPLE size macro define. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Refine riscv-vector-builtins.o include files and makefile. RISC-V: Refine riscv-vector-builtins.o include files and makefile. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Clang-format vector_type_index. RISC-V: Clang-format vector_type_index. - - - - --- 2022-10-11 Juzhe-Zhong New
RISC-V: Add new line at end of file. RISC-V: Add new line at end of file. - - - - --- 2022-10-12 Juzhe-Zhong New
RISC-V: Reorganize mangle_builtin_type.[NFC] RISC-V: Reorganize mangle_builtin_type.[NFC] - - - - --- 2022-10-14 Juzhe-Zhong New
RISC-V: Fix format[NFC] RISC-V: Fix format[NFC] - - - - --- 2022-10-17 Juzhe-Zhong New
RISC-V: Add RVV intrinsic basic framework. RISC-V: Add RVV intrinsic basic framework. - - - - --- 2022-10-17 Juzhe-Zhong New
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. - - - - --- 2022-10-17 Juzhe-Zhong New
RISC-V: Fix REG_CLASS_CONTENTS. RISC-V: Fix REG_CLASS_CONTENTS. - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF. RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF. - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Support (set (mem) (const_poly_int)) RISC-V: Support (set (mem) (const_poly_int)) - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Remove unused TI/TF vector modes. RISC-V: Remove unused TI/TF vector modes. - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Support load/store in mov<mode> pattern for RVV modes. RISC-V: Support load/store in mov<mode> pattern for RVV modes. - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Replace CONSTEXPR with constexpr RISC-V: Replace CONSTEXPR with constexpr - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Support (set (mem) (const_poly_int)) RISC-V: Support (set (mem) (const_poly_int)) - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: Fix typo. RISC-V: Fix typo. - - - - --- 2022-10-24 Juzhe-Zhong New
RISC-V: ADJUST_NUNITS according to -march. RISC-V: ADJUST_NUNITS according to -march. - - - - --- 2022-10-25 Juzhe-Zhong New
RISC-V: Fix a mistake in previous patch. RISC-V: Fix a mistake in previous patch. - - - - --- 2022-10-25 Juzhe-Zhong New
RISC-V: Change constexpr back to CONSTEXPR RISC-V: Change constexpr back to CONSTEXPR - - - - --- 2022-10-27 Juzhe-Zhong New
RISC-V: Fix RVV testcases. RISC-V: Fix RVV testcases. - - - - --- 2022-10-31 Juzhe-Zhong New
RISC-V: Add RVV registers register spilling RISC-V: Add RVV registers register spilling - - - - --- 2022-11-06 Juzhe-Zhong New
RISC-V: Add duplicate vector support. RISC-V: Add duplicate vector support. - - - - --- 2022-11-25 Juzhe-Zhong New
RISC-V: Add attributes for VSETVL PASS RISC-V: Add attributes for VSETVL PASS - - - - --- 2022-11-28 Juzhe-Zhong New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - - --- 2022-11-28 Juzhe-Zhong New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - - --- 2022-11-29 Juzhe-Zhong New
RISC-V: Fix RVV mask mode size RISC-V: Fix RVV mask mode size - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Change vlmul printing rule RISC-V: Change vlmul printing rule - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Fix RVV machine mode attribute configuration RISC-V: Fix RVV machine mode attribute configuration - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Add testcases for VSETVL PASS RISC-V: Add testcases for VSETVL PASS - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Add testcases for VSETVL PASS 2 RISC-V: Add testcases for VSETVL PASS 2 - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Add testcases for VSETVL PASS 3 RISC-V: Add testcases for VSETVL PASS 3 - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Add testcases for VSETVL PASS 4 RISC-V: Add testcases for VSETVL PASS 4 - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Add testcases for VSETVL PASS 5 RISC-V: Add testcases for VSETVL PASS 5 - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Fix annotation RISC-V: Fix annotation - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Remove unused redundant vector attributes RISC-V: Remove unused redundant vector attributes - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Remove unit-stride store from ta attribute RISC-V: Remove unit-stride store from ta attribute - - - - --- 2022-12-14 Juzhe-Zhong New
RISC-V: Simplify ASM checks. RISC-V: Simplify ASM checks. - - - - --- 2022-12-19 Juzhe-Zhong New
RISC-V: Simplify ASM checks 2 RISC-V: Simplify ASM checks 2 - - - - --- 2022-12-19 Juzhe-Zhong New
RISC-V: Fix muti-line condition format RISC-V: Fix muti-line condition format - - - - --- 2022-12-19 Juzhe-Zhong New
RISC-V: Fix incorrect annotation RISC-V: Fix incorrect annotation - - - - --- 2022-12-19 Juzhe-Zhong New
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties - - - - --- 2022-12-20 Juzhe-Zhong New
RISC-V: Remove side effects of vsetvl pattern in RTL. RISC-V: Remove side effects of vsetvl pattern in RTL. - - - - --- 2022-12-20 Juzhe-Zhong New
RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. - - - - --- 2022-12-20 Juzhe-Zhong New
RISC-V: Support vle.v/vse.v intrinsics RISC-V: Support vle.v/vse.v intrinsics - - - - --- 2022-12-23 Juzhe-Zhong New
RISC-V: Fix vle constraints RISC-V: Fix vle constraints - - - - --- 2022-12-23 Juzhe-Zhong New
RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. - - - - --- 2022-12-23 Juzhe-Zhong New
RISC-V: Fix ICE of visiting non-existing block in CFG. RISC-V: Fix ICE of visiting non-existing block in CFG. - - - - --- 2022-12-24 Juzhe-Zhong New
RISC-V: Fix pointer tree type for store pointer. RISC-V: Fix pointer tree type for store pointer. - - - - --- 2022-12-28 Juzhe-Zhong New
RISC-V: Change form of iterating blocks RISC-V: Change form of iterating blocks - - - - --- 2022-12-28 Juzhe-Zhong New
RISC-V: Fix inferior codegen for vse intrinsics. RISC-V: Fix inferior codegen for vse intrinsics. - - - - --- 2022-12-29 Juzhe-Zhong New
RISC-V: Fix vsetivli instruction asm for IMM AVL RISC-V: Fix vsetivli instruction asm for IMM AVL - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Fix wrong in_group flag in validate_change call function RISC-V: Fix wrong in_group flag in validate_change call function - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Fix backward_propagate_worthwhile_p RISC-V: Fix backward_propagate_worthwhile_p - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Simplify codes of changing vsetvl instruction RISC-V: Simplify codes of changing vsetvl instruction - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Fix bugs of available condition. RISC-V: Fix bugs of available condition. - - - - --- 2023-01-03 Juzhe-Zhong New
RISC-V: Refine Phase 3 of VSETVL PASS RISC-V: Refine Phase 3 of VSETVL PASS - - - - --- 2023-01-04 Juzhe-Zhong New
RISC-V: Add testcases for IMM (0 ~ 31) AVL RISC-V: Add testcases for IMM (0 ~ 31) AVL - - - - --- 2023-01-04 Juzhe-Zhong New
RISC-V: Cleanup the codes of bitmap create and free [NFC] RISC-V: Cleanup the codes of bitmap create and free [NFC] - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Avoid redundant flow in forward fusion RISC-V: Avoid redundant flow in forward fusion - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Refine codes in backward fusion RISC-V: Refine codes in backward fusion - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Avoid redundant flow in backward fusion RISC-V: Avoid redundant flow in backward fusion - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Rename insn into rinsn for rtx_insn * RISC-V: Rename insn into rinsn for rtx_insn * - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Add probability model of each block to prevent endless loop of Phase 3 RISC-V: Add probability model of each block to prevent endless loop of Phase 3 - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Call DCE to remove redundant instructions created by the PASS RISC-V: Call DCE to remove redundant instructions created by the PASS - - - - --- 2023-01-09 Juzhe-Zhong New
RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS - - - - --- 2023-01-09 Juzhe-Zhong New
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