Show patches with: State = Action Required       |   127026 patches
« 1 2 ... 209 210 211 … 1270 1271 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[x86_64] Decrement followed by cmov improvements. [x86_64] Decrement followed by cmov improvements. - - - - --- 2021-07-26 Roger Sayle New
Fold (X<<C1)^(X<<C2) to a multiplication when possible. Fold (X<<C1)^(X<<C2) to a multiplication when possible. - - - - --- 2021-07-26 Roger Sayle New
[take,2] Fold (X<<C1)^(X<<C2) to a multiplication when possible. [take,2] Fold (X<<C1)^(X<<C2) to a multiplication when possible. - - - - --- 2021-07-28 Roger Sayle New
Optimize x ? bswap(x) : 0 in tree-ssa-phiopt Optimize x ? bswap(x) : 0 in tree-ssa-phiopt - - - - --- 2021-07-31 Roger Sayle New
[Committed] Use CFN_BUILT_IN_CLRSB instead of BUILT_IN_CLRSB in switch. [Committed] Use CFN_BUILT_IN_CLRSB instead of BUILT_IN_CLRSB in switch. - - - - --- 2021-08-06 Roger Sayle New
Improve handling of unknown sign bit in CCP. Improve handling of unknown sign bit in CCP. - - - - --- 2021-08-08 Roger Sayle New
Recognize highpart multiplication during RTL expansion Recognize highpart multiplication during RTL expansion - - - - --- 2021-08-08 Roger Sayle New
Improved handling of MULT_EXPR in bit CCP. Improved handling of MULT_EXPR in bit CCP. - - - - --- 2021-08-09 Roger Sayle New
Improved handling of MINUS_EXPR in bit CCP. Improved handling of MINUS_EXPR in bit CCP. - - - - --- 2021-08-12 Roger Sayle New
Fold more constants during veclower pass. Fold more constants during veclower pass. - - - - --- 2021-08-19 Roger Sayle New
nvptx: Add a __PTX_ISA__ predefined macro based on target ISA. nvptx: Add a __PTX_ISA__ predefined macro based on target ISA. - - - - --- 2021-08-19 Roger Sayle New
Simplify (truncate:QI (subreg:SI (reg:QI x))) to (reg:QI x) Simplify (truncate:QI (subreg:SI (reg:QI x))) to (reg:QI x) - - - - --- 2021-08-19 Roger Sayle New
Improved handling of shifts/rotates in bit CCP. Improved handling of shifts/rotates in bit CCP. - - - - --- 2021-08-22 Roger Sayle New
Improved handling of division/modulus in bit CCP. Improved handling of division/modulus in bit CCP. - - - - --- 2021-08-22 Roger Sayle New
Fold sign of LSHIFT_EXPR to eliminate no-op conversions. Fold sign of LSHIFT_EXPR to eliminate no-op conversions. - - - - --- 2021-08-23 Roger Sayle New
[Committed] Restore build on !TARGET_TRULY_NOOP_TRUNCATION targets [Committed] Restore build on !TARGET_TRULY_NOOP_TRUNCATION targets - - - - --- 2021-08-23 Roger Sayle New
[Committed] PR middle-end/102029: Stricter typing in LSHIFT_EXPR sign folding. [Committed] PR middle-end/102029: Stricter typing in LSHIFT_EXPR sign folding. - - - - --- 2021-08-24 Roger Sayle New
[Committed] PR middle-end/102031: Fix typo/mistake in simplify_truncation patch [Committed] PR middle-end/102031: Fix typo/mistake in simplify_truncation patch - - - - --- 2021-08-24 Roger Sayle New
[Committed] Tidy up !POINTER_TYPE_P test in match.pd LSHIFT_EXPR folding [Committed] Tidy up !POINTER_TYPE_P test in match.pd LSHIFT_EXPR folding - - - - --- 2021-08-26 Roger Sayle New
nvptx: Use cvt to perform sign-extension of truncation. nvptx: Use cvt to perform sign-extension of truncation. - - - - --- 2021-08-27 Roger Sayle New
Only simplify TRUNCATE to SUBREG on TRULY_NOOP_TRUNCATION targets Only simplify TRUNCATE to SUBREG on TRULY_NOOP_TRUNCATION targets - - - - --- 2021-08-27 Roger Sayle New
Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))) Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))) - - - - --- 2021-08-29 Roger Sayle New
PR middle-end/100810: Penalize IV candidates with undefined value bases PR middle-end/100810: Penalize IV candidates with undefined value bases - - - - --- 2021-08-31 Roger Sayle New
C: PR c/79412: Poison decls with error_mark_node after type mismatch C: PR c/79412: Poison decls with error_mark_node after type mismatch - - - - --- 2021-08-31 Roger Sayle New
Correct implementation of wi::clz Correct implementation of wi::clz - - - - --- 2021-09-05 Roger Sayle New
Simplify paradoxical subreg extensions of TRUNCATE Simplify paradoxical subreg extensions of TRUNCATE - - - - --- 2021-09-05 Roger Sayle New
More NEGATE_EXPR folding in match.pd More NEGATE_EXPR folding in match.pd - - - - --- 2021-09-09 Roger Sayle New
[Take,2] More NEGATE_EXPR folding in match.pd [Take,2] More NEGATE_EXPR folding in match.pd - - - - --- 2021-09-10 Roger Sayle New
Also preserve SUBREG_PROMOTED_VAR_P in expr.c's convert_move. Also preserve SUBREG_PROMOTED_VAR_P in expr.c's convert_move. - - - - --- 2021-09-11 Roger Sayle New
PR c/102245: Don't warn that ((_Bool)x<<0) isn't a truthvalue. PR c/102245: Don't warn that ((_Bool)x<<0) isn't a truthvalue. - - - - --- 2021-09-13 Roger Sayle New
[#2] PR c/102245: Disable sign-changing optimization for shifts by zero. [#2] PR c/102245: Disable sign-changing optimization for shifts by zero. - - - - --- 2021-09-14 Roger Sayle New
nvptx: Add (experimental) support for HFmode with -misa=sm_53 nvptx: Add (experimental) support for HFmode with -misa=sm_53 - - - - --- 2021-09-16 Roger Sayle New
nvptx: Adds uses of -misa=sm_75 and -misa=sm_80 nvptx: Adds uses of -misa=sm_75 and -misa=sm_80 - - - - --- 2021-09-17 Roger Sayle New
PR middle-end/88173: More constant folding of NaN comparisons. PR middle-end/88173: More constant folding of NaN comparisons. - - - - --- 2021-09-18 Roger Sayle New
[RFC/PATCH] C++ constexpr vs. floating point exceptions. [RFC/PATCH] C++ constexpr vs. floating point exceptions. - - - - --- 2021-09-21 Roger Sayle New
Make flag_trapping_math a non-binary Boolean. Make flag_trapping_math a non-binary Boolean. - - - - --- 2021-09-25 Roger Sayle New
Introduce sh_mul and uh_mul RTX codes for high-part multiplications Introduce sh_mul and uh_mul RTX codes for high-part multiplications - - - - --- 2021-09-25 Roger Sayle New
[RFC] Experimental __attribute__((saturating)) on integer types. [RFC] Experimental __attribute__((saturating)) on integer types. - - - - --- 2021-09-26 Roger Sayle New
[#2] Introduce smul_highpart and umul_highpart RTX for high-part multiplications [#2] Introduce smul_highpart and umul_highpart RTX for high-part multiplications - - - - --- 2021-09-29 Roger Sayle New
Try placing RTL folded constants in constant pool Try placing RTL folded constants in constant pool - - - - --- 2021-10-03 Roger Sayle New
Transition nvptx backend to STORE_FLAG_VALUE = 1 Transition nvptx backend to STORE_FLAG_VALUE = 1 - - - - --- 2021-10-05 Roger Sayle New
[Committed] Tweak new test cases for -march=cascadelake strangeness. [Committed] Tweak new test cases for -march=cascadelake strangeness. - - - - --- 2021-10-08 Roger Sayle New
x86_64: Some SUBREG related optimization tweaks to i386 backend. x86_64: Some SUBREG related optimization tweaks to i386 backend. - - - - --- 2021-10-11 Roger Sayle New
[v2] x86_64: Some SUBREG related optimization tweaks to i386 backend. [v2] x86_64: Some SUBREG related optimization tweaks to i386 backend. - - - - --- 2021-10-13 Roger Sayle New
Allow early sets of SSE hard registers from standard_sse_constant_p Allow early sets of SSE hard registers from standard_sse_constant_p - - - - --- 2021-10-15 Roger Sayle New
Constant fold SS_NEG and SS_ABS in simplify-rtx.c Constant fold SS_NEG and SS_ABS in simplify-rtx.c - - - - --- 2021-10-17 Roger Sayle New
bfin: Popcount-related improvements to machine description. bfin: Popcount-related improvements to machine description. - - - - --- 2021-10-17 Roger Sayle New
PR target/102785: Correct addsub/subadd patterns on bfin. PR target/102785: Correct addsub/subadd patterns on bfin. - - - - --- 2021-10-18 Roger Sayle New
x86_64: Add insn patterns for V1TI mode logic operations. x86_64: Add insn patterns for V1TI mode logic operations. - - - - --- 2021-10-22 Roger Sayle New
[Committed] Correct testcase gcc.target/bfin/20090914-3.c [Committed] Correct testcase gcc.target/bfin/20090914-3.c - - - - --- 2021-10-24 Roger Sayle New
x86_64: Implement V1TI mode shifts/rotates by a constant x86_64: Implement V1TI mode shifts/rotates by a constant - - - - --- 2021-10-24 Roger Sayle New
Constant fold/simplify SS_ASHIFT and US_ASHIFT in simplify-rtx.c Constant fold/simplify SS_ASHIFT and US_ASHIFT in simplify-rtx.c - - - - --- 2021-10-25 Roger Sayle New
x86_64: Expand ashrv1ti (and PR target/102986) x86_64: Expand ashrv1ti (and PR target/102986) - - - - --- 2021-10-30 Roger Sayle New
[Take,#2] x86_64: Expand ashrv1ti (and PR target/102986) [Take,#2] x86_64: Expand ashrv1ti (and PR target/102986) - - - - --- 2021-10-31 Roger Sayle New
x86_64: Improved implementation of TImode rotations. x86_64: Improved implementation of TImode rotations. - - - - --- 2021-11-01 Roger Sayle New
ivopts: Improve code generated for very simple loops. ivopts: Improve code generated for very simple loops. - - - - --- 2021-11-15 Roger Sayle New
x86_64: Avoid rorx rotation instructions with -Os x86_64: Avoid rorx rotation instructions with -Os - - - - --- 2021-11-15 Roger Sayle New
[take,2] ivopts: Improve code generated for very simple loops. [take,2] ivopts: Improve code generated for very simple loops. - - - - --- 2021-11-18 Roger Sayle New
Tweak tree-ssa-math-opts.c to solve PR target/102117 Tweak tree-ssa-math-opts.c to solve PR target/102117 - - - - --- 2021-11-20 Roger Sayle New
tree-optimization/103345: Improved load merging tree-optimization/103345: Improved load merging - - - - --- 2021-11-22 Roger Sayle New
PR middle-end/103406: Check for Inf before simplifying x-x. PR middle-end/103406: Check for Inf before simplifying x-x. - - - - --- 2021-11-25 Roger Sayle New
[take,3] ivopts: Improve code generated for very simple loops. [take,3] ivopts: Improve code generated for very simple loops. - - - - --- 2021-11-25 Roger Sayle New
x86_64: PR target/100711: Splitters for pandn x86_64: PR target/100711: Splitters for pandn - - - - --- 2021-11-28 Roger Sayle New
x86_64: Improved V1TImode rotations by non-constant amounts. x86_64: Improved V1TImode rotations by non-constant amounts. - - - - --- 2021-11-28 Roger Sayle New
Final value replacement improvements for until-wrap loops. Final value replacement improvements for until-wrap loops. - - - - --- 2021-11-29 Roger Sayle New
[take,#2] x86_64: PR target/100711: Splitters for pandn [take,#2] x86_64: PR target/100711: Splitters for pandn - - - - --- 2021-11-29 Roger Sayle New
[Committed] PR testsuite/103477: Fix big-endian mistake in new test case. [Committed] PR testsuite/103477: Fix big-endian mistake in new test case. - - - - --- 2021-11-30 Roger Sayle New
[take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. [take,#2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. - - - - --- 2021-12-03 Roger Sayle New
PR ipa/103601: ICE compiling CSiBE in ipa-modref's insert_kill PR ipa/103601: ICE compiling CSiBE in ipa-modref's insert_kill - - - - --- 2021-12-10 Roger Sayle New
x86_64: Improve code expanded for highpart multiplications. x86_64: Improve code expanded for highpart multiplications. - - - - --- 2021-12-10 Roger Sayle New
Improved handling of REG_UNUSED notes on PARALLEL in try_combine. Improved handling of REG_UNUSED notes on PARALLEL in try_combine. - - - - --- 2021-12-10 Roger Sayle New
mips: Improved RTL representation of wsbh/dsbh/dshd mips: Improved RTL representation of wsbh/dsbh/dshd - - - - --- 2021-12-10 Roger Sayle New
PR target/32803: Add -Oz option for improved clang compatibility. PR target/32803: Add -Oz option for improved clang compatibility. - - - - --- 2021-12-10 Roger Sayle New
PR target/103611: Avoid generating orb $0, %ah on x86. PR target/103611: Avoid generating orb $0, %ah on x86. - - - - --- 2021-12-13 Roger Sayle New
x86: PR target/103611: Splitter for DST:DI = (HI:SI<<32)|LO:SI. x86: PR target/103611: Splitter for DST:DI = (HI:SI<<32)|LO:SI. - - - - --- 2021-12-13 Roger Sayle New
[take,#2] x86_64: Improve code expanded for highpart multiplications. [take,#2] x86_64: Improve code expanded for highpart multiplications. - - - - --- 2021-12-20 Roger Sayle New
PR target/103773: Fix wrong-code with -Oz from pop to memory. PR target/103773: Fix wrong-code with -Oz from pop to memory. - - - - --- 2021-12-21 Roger Sayle New
x86: Shrink writing 0/-1 to memory using and/or with -Oz. x86: Shrink writing 0/-1 to memory using and/or with -Oz. - - - - --- 2021-12-21 Roger Sayle New
[take,#3] PR target/103773: Fix wrong-code with -Oz from pop to memory. [take,#3] PR target/103773: Fix wrong-code with -Oz from pop to memory. - - - - --- 2021-12-23 Roger Sayle New
nvptx: Add support for PTX's cnot instruction. nvptx: Add support for PTX's cnot instruction. - - - - --- 2022-01-06 Roger Sayle New
x86_64: Improve (interunit) moves from TImode to V1TImode. x86_64: Improve (interunit) moves from TImode to V1TImode. - - - - --- 2022-01-06 Roger Sayle New
[take,#3] Recognize MULT_HIGHPART_EXPR in tree-ssa-math-opts pass. [take,#3] Recognize MULT_HIGHPART_EXPR in tree-ssa-math-opts pass. - - - - --- 2022-01-06 Roger Sayle New
nvptx: Improved support for HFMode including neghf2 and abshf2. nvptx: Improved support for HFMode including neghf2 and abshf2. - - - - --- 2022-01-08 Roger Sayle New
nvptx: Expand QI mode operations using SI mode instructions. nvptx: Expand QI mode operations using SI mode instructions. - - - - --- 2022-01-10 Roger Sayle New
x86_64: Improvements to arithmetic right shifts of V1TImode values. x86_64: Improvements to arithmetic right shifts of V1TImode values. - - - - --- 2022-01-11 Roger Sayle New
nvptx: Add support for 64-bit mul.hi (and other) instructions. nvptx: Add support for 64-bit mul.hi (and other) instructions. - - - - --- 2022-01-14 Roger Sayle New
nvptx: Fix and use BI mode logic instructions (e.g. and.pred). nvptx: Fix and use BI mode logic instructions (e.g. and.pred). - - - - --- 2022-01-16 Roger Sayle New
PR middle-end/104140: bootstrap ICE on riscv. PR middle-end/104140: bootstrap ICE on riscv. - - - - --- 2022-01-21 Roger Sayle New
PR tree-optimization/102950: Improved EVRP for signed BIT_XOR_EXPR. PR tree-optimization/102950: Improved EVRP for signed BIT_XOR_EXPR. - - - - --- 2022-02-01 Roger Sayle New
PR rtl-optimization/101885: Prevent combine from clobbering flags PR rtl-optimization/101885: Prevent combine from clobbering flags - - - - --- 2022-02-03 Roger Sayle New
PR target/104345: Use nvptx "set" instruction for cond ? -1 : 0. PR target/104345: Use nvptx "set" instruction for cond ? -1 : 0. - - - - --- 2022-02-03 Roger Sayle New
nvptx: Tweak constraints on copysign instructions. nvptx: Tweak constraints on copysign instructions. - - - - --- 2022-02-08 Roger Sayle New
PR tree-optimization/104420: Fix checks for constant folding X*0.0 PR tree-optimization/104420: Fix checks for constant folding X*0.0 - - - - --- 2022-02-08 Roger Sayle New
middle-end: Support ABIs that pass FP values as wider integers. middle-end: Support ABIs that pass FP values as wider integers. - - - - --- 2022-02-09 Roger Sayle New
gfortran: Respect target's NO_DOT_IN_LABEL in trans-common.cc gfortran: Respect target's NO_DOT_IN_LABEL in trans-common.cc - - - - --- 2022-02-10 Roger Sayle New
nvptx: Back-end portion of a fix for PR target/104489. nvptx: Back-end portion of a fix for PR target/104489. - - - - --- 2022-02-11 Roger Sayle New
PR c/104506: Tolerate error_mark_node in useless_type_conversion_p. PR c/104506: Tolerate error_mark_node in useless_type_conversion_p. - - - - --- 2022-02-14 Roger Sayle New
PR middle-end/65855: Scalar evolution for quadratic chrecs PR middle-end/65855: Scalar evolution for quadratic chrecs - - - - --- 2022-02-18 Roger Sayle New
Improved constant folding for scalar evolution. Improved constant folding for scalar evolution. - - - - --- 2022-02-20 Roger Sayle New
PR tree-optimization/83907: Improved memset handling in strlen pass. PR tree-optimization/83907: Improved memset handling in strlen pass. - - - - --- 2022-02-20 Roger Sayle New
« 1 2 ... 209 210 211 … 1270 1271 »