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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[13/21] Adjust scalable frame and full testcases
*** Add RVV (RISC-V 'V' Extension) support ***
- - - -
-
-
-
2022-05-31
juzhe.zhong@rivai.ai
New
[15/21] Add integer intrinsics
*** Add RVV (RISC-V 'V' Extension) support ***
- - - -
-
-
-
2022-05-31
juzhe.zhong@rivai.ai
New
[18/21] Add rest intrinsic support
*** Add RVV (RISC-V 'V' Extension) support ***
- - - -
-
-
-
2022-05-31
juzhe.zhong@rivai.ai
New
[v2,1/1] Add unit-stride load store intrinsics
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-05-31
juzhe.zhong@rivai.ai
New
[v3] RISC-V: Add load and store intrinsics support for RVV support
[v3] RISC-V: Add load and store intrinsics support for RVV support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,02/34] RISC-V: Add vlex_2.c
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,03/34] RISC-V: Add vlex_1.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,04/34] RISC-V: Add mask load store testcases
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,06/34] RISC-V: Add vlexff_2.c
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,12/34] RISC-V: Add vlsex_2.c
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,17/34] RISC-V: Add vsex.c
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,19/34] RISC-V: Add vssex.c
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,21/34] RISC-V: Add vlexff_1.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,22/34] RISC-V: Add vloxeix_1.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,23/34] RISC-V: Add vloxeix_2.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,24/34] RISC-V: Add vloxeix_3.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,25/34] RISC-V: Add vloxeix_4.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,26/34] RISC-V: Add vlsex_1.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,27/34] RISC-V: Add vluxeix_1.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,28/34] RISC-V: Add vluxeix_2.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,29/34] RISC-V: Add vluxeix_3.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,30/34] RISC-V: Add vluxeix_4.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,31/34] RISC-V: Add vsex.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,32/34] RISC-V: Add vsoxeix.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,33/34] RISC-V: Add vssex.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[v4,34/34] RISC-V: Add vsuxeix.C
RISC-V: Add RVV (RISC-V 'V' Extension) support
- - - -
-
-
-
2022-06-01
juzhe.zhong@rivai.ai
New
[1/1] Fix bit-position comparison
middle-end: Fix bit position comparison
- - - -
-
-
-
2022-07-27
juzhe.zhong@rivai.ai
New
RISC-V: Add runtime invariant support
RISC-V: Add runtime invariant support
- - - -
-
-
-
2022-08-17
juzhe.zhong@rivai.ai
New
middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with…
middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with…
- - - -
-
-
-
2022-08-18
juzhe.zhong@rivai.ai
New
middle-end: Fix issue of poly_uint16 (1, 1) in self test
middle-end: Fix issue of poly_uint16 (1, 1) in self test
- - - -
-
-
-
2022-08-22
juzhe.zhong@rivai.ai
New
middle-end: Fix unexpected warnings for RISC-V port.
middle-end: Fix unexpected warnings for RISC-V port.
- - - -
-
-
-
2022-08-23
juzhe.zhong@rivai.ai
New
RISC-V: Add vector registers and classification
RISC-V: Add vector registers and classification
- - - -
-
-
-
2022-08-26
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV instructions classification
RISC-V: Add RVV instructions classification
- - - -
-
-
-
2022-08-27
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers
RISC-V: Add RVV registers
- - - -
-
-
-
2022-08-27
juzhe.zhong@rivai.ai
New
RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN
RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Fix annotation
RISC-V: Fix annotation
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV constraints.
RISC-V: Add RVV constraints.
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add csrr vlenb instruction.
RISC-V: Add csrr vlenb instruction.
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE
- - - -
-
-
-
2022-08-30
juzhe.zhong@rivai.ai
New
RISC-V: Support poly move manipulation and selftests.
RISC-V: Support poly move manipulation and selftests.
- - - -
-
-
-
2022-09-15
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV machine modes.
RISC-V: Add RVV machine modes.
- - - -
-
-
-
2022-09-15
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV machine modes.
RISC-V: Add RVV machine modes.
- - - -
-
-
-
2022-09-15
juzhe.zhong@rivai.ai
New
RISC-V: Suppress riscv-selftests.cc warning.
RISC-V: Suppress riscv-selftests.cc warning.
- - - -
-
-
-
2022-09-17
juzhe.zhong@rivai.ai
New
DSE: Enhance dse with def-ref analysis
DSE: Enhance dse with def-ref analysis
- - - -
-
-
-
2022-09-22
juzhe.zhong@rivai.ai
New
DSE: Enhance dse with def-ref analysis
DSE: Enhance dse with def-ref analysis
- - - -
-
-
-
2022-09-22
juzhe.zhong@rivai.ai
New
RISC-V: Add ABI-defined RVV types.
RISC-V: Add ABI-defined RVV types.
- - - -
-
-
-
2022-09-27
juzhe.zhong@rivai.ai
New
[Unfinished] Add first-order recurrence autovectorization
[Unfinished] Add first-order recurrence autovectorization
- - - -
-
-
-
2022-09-29
juzhe.zhong@rivai.ai
New
RISC-V: Introduce RVV header to enable builtin types
RISC-V: Introduce RVV header to enable builtin types
- - - -
-
-
-
2022-09-30
juzhe.zhong@rivai.ai
New
Add first-order recurrence autovectorization
Add first-order recurrence autovectorization
- - - -
-
-
-
2022-09-30
juzhe.zhong@rivai.ai
New
RISC-V: Add missing vsetvl instruction type.
RISC-V: Add missing vsetvl instruction type.
- - - -
-
-
-
2022-10-10
juzhe.zhong@rivai.ai
New
RISC-V: move struct vector_type_info from *.h to *.cc.
RISC-V: move struct vector_type_info from *.h to *.cc.
- - - -
-
-
-
2022-10-10
juzhe.zhong@rivai.ai
New
RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".
RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".
- - - -
-
-
-
2022-10-10
juzhe.zhong@rivai.ai
New
RISC-V: Move function place to make it looks better.
RISC-V: Move function place to make it looks better.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Refine register_builtin_types function.
RISC-V: Refine register_builtin_types function.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Clang-format add_vector_attribute function.
RISC-V: Clang-format add_vector_attribute function.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Remove TUPLE size macro define.
RISC-V: Remove TUPLE size macro define.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Refine riscv-vector-builtins.o include files and makefile.
RISC-V: Refine riscv-vector-builtins.o include files and makefile.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Clang-format vector_type_index.
RISC-V: Clang-format vector_type_index.
- - - -
-
-
-
2022-10-11
juzhe.zhong@rivai.ai
New
RISC-V: Add new line at end of file.
RISC-V: Add new line at end of file.
- - - -
-
-
-
2022-10-12
juzhe.zhong@rivai.ai
New
RISC-V: Reorganize mangle_builtin_type.[NFC]
RISC-V: Reorganize mangle_builtin_type.[NFC]
- - - -
-
-
-
2022-10-14
juzhe.zhong@rivai.ai
New
RISC-V: Fix format[NFC]
RISC-V: Fix format[NFC]
- - - -
-
-
-
2022-10-17
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV intrinsic basic framework.
RISC-V: Add RVV intrinsic basic framework.
- - - -
-
-
-
2022-10-17
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.
- - - -
-
-
-
2022-10-17
juzhe.zhong@rivai.ai
New
RISC-V: Fix REG_CLASS_CONTENTS.
RISC-V: Fix REG_CLASS_CONTENTS.
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF.
RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF.
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Support (set (mem) (const_poly_int))
RISC-V: Support (set (mem) (const_poly_int))
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Remove unused TI/TF vector modes.
RISC-V: Remove unused TI/TF vector modes.
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Support load/store in mov<mode> pattern for RVV modes.
RISC-V: Support load/store in mov<mode> pattern for RVV modes.
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Replace CONSTEXPR with constexpr
RISC-V: Replace CONSTEXPR with constexpr
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Support (set (mem) (const_poly_int))
RISC-V: Support (set (mem) (const_poly_int))
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: Fix typo.
RISC-V: Fix typo.
- - - -
-
-
-
2022-10-24
juzhe.zhong@rivai.ai
New
RISC-V: ADJUST_NUNITS according to -march.
RISC-V: ADJUST_NUNITS according to -march.
- - - -
-
-
-
2022-10-25
juzhe.zhong@rivai.ai
New
RISC-V: Fix a mistake in previous patch.
RISC-V: Fix a mistake in previous patch.
- - - -
-
-
-
2022-10-25
juzhe.zhong@rivai.ai
New
RISC-V: Change constexpr back to CONSTEXPR
RISC-V: Change constexpr back to CONSTEXPR
- - - -
-
-
-
2022-10-27
juzhe.zhong@rivai.ai
New
RISC-V: Fix RVV testcases.
RISC-V: Fix RVV testcases.
- - - -
-
-
-
2022-10-31
juzhe.zhong@rivai.ai
New
RISC-V: Add RVV registers register spilling
RISC-V: Add RVV registers register spilling
- - - -
-
-
-
2022-11-06
juzhe.zhong@rivai.ai
New
RISC-V: Add duplicate vector support.
RISC-V: Add duplicate vector support.
- - - -
-
-
-
2022-11-25
juzhe.zhong@rivai.ai
New
RISC-V: Add attributes for VSETVL PASS
RISC-V: Add attributes for VSETVL PASS
- - - -
-
-
-
2022-11-28
juzhe.zhong@rivai.ai
New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
- - - -
-
-
-
2022-11-28
juzhe.zhong@rivai.ai
New
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst
- - - -
-
-
-
2022-11-29
juzhe.zhong@rivai.ai
New
RISC-V: Fix RVV mask mode size
RISC-V: Fix RVV mask mode size
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Change vlmul printing rule
RISC-V: Change vlmul printing rule
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Fix RVV machine mode attribute configuration
RISC-V: Fix RVV machine mode attribute configuration
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Support VSETVL PASS for RVV support
RISC-V: Support VSETVL PASS for RVV support
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Support VSETVL PASS for RVV support
RISC-V: Support VSETVL PASS for RVV support
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Support VSETVL PASS for RVV support
RISC-V: Support VSETVL PASS for RVV support
- - - -
-
-
-
2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for VSETVL PASS
RISC-V: Add testcases for VSETVL PASS
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for VSETVL PASS 2
RISC-V: Add testcases for VSETVL PASS 2
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for VSETVL PASS 3
RISC-V: Add testcases for VSETVL PASS 3
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for VSETVL PASS 4
RISC-V: Add testcases for VSETVL PASS 4
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Add testcases for VSETVL PASS 5
RISC-V: Add testcases for VSETVL PASS 5
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Fix annotation
RISC-V: Fix annotation
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Remove unused redundant vector attributes
RISC-V: Remove unused redundant vector attributes
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Remove unit-stride store from ta attribute
RISC-V: Remove unit-stride store from ta attribute
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2022-12-14
juzhe.zhong@rivai.ai
New
RISC-V: Simplify ASM checks.
RISC-V: Simplify ASM checks.
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2022-12-19
juzhe.zhong@rivai.ai
New
RISC-V: Simplify ASM checks 2
RISC-V: Simplify ASM checks 2
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2022-12-19
juzhe.zhong@rivai.ai
New
RISC-V: Fix muti-line condition format
RISC-V: Fix muti-line condition format
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2022-12-19
juzhe.zhong@rivai.ai
New
RISC-V: Fix incorrect annotation
RISC-V: Fix incorrect annotation
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2022-12-19
juzhe.zhong@rivai.ai
New
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties
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2022-12-20
juzhe.zhong@rivai.ai
New
RISC-V: Remove side effects of vsetvl pattern in RTL.
RISC-V: Remove side effects of vsetvl pattern in RTL.
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2022-12-20
juzhe.zhong@rivai.ai
New
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