Show patches with: State = Action Required       |    Archived = No       |   126536 patches
« 1 2 ... 602 603 604 … 1265 1266 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes [Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes - - - - --- 2023-12-28 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis [Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis - - - - --- 2023-12-22 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Format VSETVL PASS code [Committed] RISC-V: Format VSETVL PASS code - - - - --- 2023-09-14 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Force scalable vector on all vsetvl tests [Committed] RISC-V: Force scalable vector on all vsetvl tests - - - - --- 2023-12-19 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix vsingle attribute [Committed] RISC-V: Fix vsingle attribute - - - - --- 2023-10-15 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix typo[VSETVL PASS] [Committed] RISC-V: Fix typo[VSETVL PASS] - - - - --- 2023-10-23 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix typo [Committed] RISC-V: Fix typo - - - - --- 2023-11-26 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix typo [Committed] RISC-V: Fix typo - - - - --- 2023-12-26 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix regression [Committed] RISC-V: Fix regression - - - - --- 2024-01-30 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix redundant attributes [Committed] RISC-V: Fix redundant attributes - - - - --- 2023-11-02 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix reduc_run-9.c test value check bug [Committed] RISC-V: Fix reduc_run-9.c test value check bug - - - - --- 2023-11-21 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] - - - - --- 2023-09-26 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix init-2.c assembly check [Committed] RISC-V: Fix init-2.c assembly check - - - - --- 2023-11-14 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix indent [Committed] RISC-V: Fix indent - - - - --- 2024-01-03 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix dynamic tests [NFC] [Committed] RISC-V: Fix dynamic tests [NFC] - - - - --- 2023-11-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC] [Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC] - - - - --- 2024-01-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix comments of segment load/store intrinsic [Committed] RISC-V: Fix comments of segment load/store intrinsic - - - - --- 2024-01-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix bug of vlds attribute [Committed] RISC-V: Fix bug of vlds attribute - - - - --- 2023-11-05 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix bogus FAILs of vsetvl testcases [Committed] RISC-V: Fix bogus FAILs of vsetvl testcases - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix attributes bug configuration of ternary instructions [Committed] RISC-V: Fix attributes bug configuration of ternary instructions - - - - --- 2024-01-15 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix VSETVL VL check condition bug [Committed] RISC-V: Fix VSETVL VL check condition bug - - - - --- 2023-11-08 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix VSETVL PASS fusion bug [Committed] RISC-V: Fix VSETVL PASS fusion bug - - - - --- 2023-09-18 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix VLS mode movmiaslign bug [Committed] RISC-V: Fix VLS mode movmiaslign bug - - - - --- 2023-12-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix VLS floating-point operations predicate [Committed] RISC-V: Fix VLS floating-point operations predicate - - - - --- 2023-09-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix PR112888 ICE [Committed] RISC-V: Fix PR112888 ICE - - - - --- 2023-12-06 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 syste… [Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 syste… - - - - --- 2023-12-20 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] [Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] - - - - --- 2023-10-24 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix ICE in non-canonical march parsing [Committed] RISC-V: Fix ICE in non-canonical march parsing - - - - --- 2023-11-15 Patrick O'Neill New
[Committed] RISC-V: Fix ICE in extract_single_source [Committed] RISC-V: Fix ICE in extract_single_source - - - - --- 2023-12-11 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix FAIL of dynamic-lmul2-7.c [Committed] RISC-V: Fix FAIL of dynamic-lmul2-7.c - - - - --- 2023-12-19 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] - - - - --- 2023-09-20 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap [Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap - - - 1 --- 2023-09-19 Patrick O'Neill New
[Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator [Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator - - - - --- 2023-09-20 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Enhance a testcase [Committed] RISC-V: Enhance a testcase - - - - --- 2024-01-12 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Enable Hoist to GCSE simple constants [Committed] RISC-V: Enable Hoist to GCSE simple constants - - - - --- 2023-08-25 Vineet Gupta New
[Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 [Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 - - - - --- 2023-11-24 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Disable AVL propagation of slidedown instructions [Committed] RISC-V: Disable AVL propagation of slidedown instructions - - - - --- 2023-11-26 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable [Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable - - - - --- 2024-01-02 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Adjust test [Committed] RISC-V: Adjust test - - - - --- 2023-12-14 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add wrapper for emit vec_extract[NFC] [Committed] RISC-V: Add wrapper for emit vec_extract[NFC] - - - - --- 2023-11-23 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add testcase for SCCVN optimization[PR111751] [Committed] RISC-V: Add testcase for SCCVN optimization[PR111751] - - - - --- 2023-10-10 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add test for PR112469 [Committed] RISC-V: Add test for PR112469 - - - - --- 2023-11-10 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern [Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern - - - - --- 2024-01-02 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add regression test for vsetvl bug pr113429 [Committed] RISC-V: Add regression test for vsetvl bug pr113429 - - - - --- 2024-01-24 Patrick O'Neill New
[Committed] RISC-V: Add optimized dump check of VLS reduc tests [Committed] RISC-V: Add optimized dump check of VLS reduc tests - - - - --- 2024-01-15 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add optim-no-fusion compile option [VSETVL PASS] [Committed] RISC-V: Add optim-no-fusion compile option [VSETVL PASS] - - - - --- 2024-01-25 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add one more ASM check in PR113112-1.c [Committed] RISC-V: Add one more ASM check in PR113112-1.c - - - - --- 2023-12-25 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add more VLS unary tests [Committed] RISC-V: Add more VLS unary tests - - - - --- 2023-09-21 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add missing dump check of pr112438.c [Committed] RISC-V: Add missing dump check of pr112438.c - - - - --- 2023-11-21 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns [Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns - - - - --- 2023-09-11 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add failed SLP testcase [Committed] RISC-V: Add failed SLP testcase - - - - --- 2023-12-14 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add dynamic LMUL test for x264 [Committed] RISC-V: Add dynamic LMUL test for x264 - - - - --- 2023-12-21 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add VLS unary combine patterns [Committed] RISC-V: Add VLS unary combine patterns - - - - --- 2023-09-23 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add VLS integer ABS support [Committed] RISC-V: Add VLS integer ABS support - - - - --- 2023-09-21 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] [Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] - - - - --- 2023-10-10 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Add PR112450 test to avoid regression [Committed] RISC-V: Add PR112450 test to avoid regression - - - - --- 2023-11-09 juzhe.zhong@rivai.ai New
[Committed] RISC-V: Adapt VLS init tests [Committed] RISC-V: Adapt VLS init tests - - - - --- 2023-11-13 juzhe.zhong@rivai.ai New
[Committed] PowerPC PR libgcc/o7543 and libgcc/97643, Fix long double issues [Committed] PowerPC PR libgcc/o7543 and libgcc/97643, Fix long double issues - - - - --- 2020-12-04 Michael Meissner New
[Committed] PR70404 S/390: Fix insv expansion. - - - - --- 2016-04-01 Andreas Krebbel New
[Committed] PR65647 Add Missing testcase on trunk - - - - --- 2015-04-10 Yvan Roux New
[Committed] PR61123 : Fix the ABI mis-matching error caused by LTO - - - - --- 2014-06-20 Hale Wang New
[Committed] PR61123 : Fix the ABI mis-matching error caused by LTO - - - - --- 2014-06-20 Jakub Jelinek New
[Committed] PR testsuite/105486: Use "signed char" in gcc.dg/pr102950.c [Committed] PR testsuite/105486: Use "signed char" in gcc.dg/pr102950.c - - - - --- 2022-05-05 Roger Sayle New
[Committed] PR testsuite/103477: Fix big-endian mistake in new test case. [Committed] PR testsuite/103477: Fix big-endian mistake in new test case. - - - - --- 2021-11-30 Roger Sayle New
[Committed] PR target/96558: Only call ix86_expand_clear with GENERAL_REGS. [Committed] PR target/96558: Only call ix86_expand_clear with GENERAL_REGS. - - - - --- 2020-08-12 Roger Sayle New
[Committed] PR target/110843: Check TARGET_AVX512VL for V2DI rotates in STV. [Committed] PR target/110843: Check TARGET_AVX512VL for V2DI rotates in STV. - - - - --- 2023-07-31 Roger Sayle New
[Committed] PR target/110787: Revert QImode offsets in {zero, sign}_extract. [Committed] PR target/110787: Revert QImode offsets in {zero, sign}_extract. - - - - --- 2023-07-24 Roger Sayle New
[Committed] PR target/106640: Fix use of XINT in TImode compute_convert_gain. [Committed] PR target/106640: Fix use of XINT in TImode compute_convert_gain. - - - - --- 2022-08-17 Roger Sayle New
[Committed] PR other/106575: Use "signed char" in new fold-eqandshift-4.c [Committed] PR other/106575: Use "signed char" in new fold-eqandshift-4.c - - - - --- 2022-08-10 Roger Sayle New
[Committed] PR middle-end/102031: Fix typo/mistake in simplify_truncation patch [Committed] PR middle-end/102031: Fix typo/mistake in simplify_truncation patch - - - - --- 2021-08-24 Roger Sayle New
[Committed] PR middle-end/102029: Stricter typing in LSHIFT_EXPR sign folding. [Committed] PR middle-end/102029: Stricter typing in LSHIFT_EXPR sign folding. - - - - --- 2021-08-24 Roger Sayle New
[Committed] PR fortran/92897 -- remove invalid assert() [Committed] PR fortran/92897 -- remove invalid assert() - - - - --- 2019-12-11 Steve Kargl New
[Committed] PR fortran/92174 [Committed] PR fortran/92174 - - - - --- 2019-10-22 Steve Kargl New
[Committed] PR fortran/91727 -- NULL pointer dereference [Committed] PR fortran/91727 -- NULL pointer dereference - - - - --- 2019-09-15 Steve Kargl New
[Committed] PR fortran/91642 -- NULL() cannot be in iolength inquire [Committed] PR fortran/91642 -- NULL() cannot be in iolength inquire - - - - --- 2019-09-11 Steve Kargl New
[Committed] PR fortran/91641 -- is_contiguous(null()) [Committed] PR fortran/91641 -- is_contiguous(null()) - - - - --- 2019-09-29 Steve Kargl New
[Committed] PR fortran/91587 -- A syntax error should occur [Committed] PR fortran/91587 -- A syntax error should occur - - - - --- 2019-08-31 Steve Kargl New
[Committed] PR fortran/91553 -- simplification of constants needs to check for parenthesis [Committed] PR fortran/91553 -- simplification of constants needs to check for parenthesis - - - - --- 2019-09-11 Steve Kargl New
[Committed] PR fortran/91372 -- Fix parsing of DATA with implied do-loop [Committed] PR fortran/91372 -- Fix parsing of DATA with implied do-loop - - - - --- 2019-08-05 Steve Kargl New
[Committed] PR fortran/91359 -- Fix testcases that were munged [Committed] PR fortran/91359 -- Fix testcases that were munged - - - - --- 2019-08-07 Steve Kargl New
[Committed] PR fortran/90988 -- Fix. [Committed] PR fortran/90988 -- Fix. - - - - --- 2019-06-26 Steve Kargl New
[Committed] PR fortran/90985 -- DATA must be followed by whitespace [Committed] PR fortran/90985 -- DATA must be followed by whitespace - - - - --- 2019-08-02 Steve Kargl New
[Committed] PR fortran/90297 -- Don't issue EQUIVALENCE syntax error [Committed] PR fortran/90297 -- Don't issue EQUIVALENCE syntax error - - - - --- 2019-08-02 Steve Kargl New
[Committed] PR fortran/89431 -- correct documentation [Committed] PR fortran/89431 -- correct documentation - - - - --- 2019-02-22 Steve Kargl New
[Committed] PR fortran/88376 -- remove assert() [Committed] PR fortran/88376 -- remove assert() - - - - --- 2019-01-10 Steve Kargl New
[Committed] PR fortran/88357 -- NULL pointer dereferences [Committed] PR fortran/88357 -- NULL pointer dereferences - - - - --- 2018-12-08 Steve Kargl New
[Committed] PR fortran/88269 -- Check for missing UNIT/NEWUNIT [Committed] PR fortran/88269 -- Check for missing UNIT/NEWUNIT - - - - --- 2018-12-10 Steve Kargl New
[Committed] PR fortran/88249 -- Check for UNIT in file positioning [Committed] PR fortran/88249 -- Check for UNIT in file positioning - - - - --- 2018-12-11 Steve Kargl New
[Committed] PR fortran/88228 -- ICE with -fdec and logical op on integers [Committed] PR fortran/88228 -- ICE with -fdec and logical op on integers - - - - --- 2018-12-09 Steve Kargl New
[Committed] PR fortran/88206 -- Fix REAL issue with array constructor [Committed] PR fortran/88206 -- Fix REAL issue with array constructor - - - - --- 2018-12-09 Steve Kargl New
[Committed] PR fortran/88205 -- Check NEWUNIT after STATUS [Committed] PR fortran/88205 -- Check NEWUNIT after STATUS - - - - --- 2018-12-10 Steve Kargl New
[Committed] PR fortran/88155 -- Avoid NULL pointer reference [Committed] PR fortran/88155 -- Avoid NULL pointer reference - - - - --- 2018-12-12 Steve Kargl New
[Committed] PR fortran/88138 -- can't initialize a derived type [Committed] PR fortran/88138 -- can't initialize a derived type - - - - --- 2018-12-15 Steve Kargl New
[Committed] PR fortran/88048 -- named constant can't be data object [Committed] PR fortran/88048 -- named constant can't be data object - - - - --- 2018-12-09 Steve Kargl New
[Committed] PR fortran/88025 -- Null pointer no-no [Committed] PR fortran/88025 -- Null pointer no-no - - - - --- 2018-12-09 Steve Kargl New
[Committed] PR fortran/87994 -- Inquiry parameter as data constant [Committed] PR fortran/87994 -- Inquiry parameter as data constant - - - - --- 2018-12-16 Steve Kargl New
[Committed] PR fortran/87991 -- Pointer data object requires a target [Committed] PR fortran/87991 -- Pointer data object requires a target - - - - --- 2019-08-14 Steve Kargl New
[Committed] PR fortran/87945 -- Inquiry parameter in data statement [Committed] PR fortran/87945 -- Inquiry parameter in data statement - - - - --- 2018-12-09 Steve Kargl New
[Committed] PR fortran/87922 -- Additional checks for ASYNCHRONOUS [Committed] PR fortran/87922 -- Additional checks for ASYNCHRONOUS - - - - --- 2018-12-11 Steve Kargl New
[Committed] PR fortran/86110 -- Avoid NULL pointer dereference [Committed] PR fortran/86110 -- Avoid NULL pointer dereference - - - - --- 2018-06-13 Steve Kargl New
« 1 2 ... 602 603 604 … 1265 1266 »