Show patches with: Archived = No       |   126792 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v3,06/11] riscv: thead: Add support for the XTheadCondMov ISA extensions RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,06/11] c: Turn -Wimplicit-function-declaration into a permerror : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,06/11] OpenMP: Pointers and member mappings OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,06/10] testsuite: Remove PRU from test cases requiring hosted environment New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,06/10] RISCV: Eliminate AMO op fences RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,06/10] GCN back-end config AMD GCN Port v3 - - - - --- 2018-12-12 Andrew Stubbs New
[v3,05/18] convert the C front end to automatic dependencies - - - - --- 2013-08-20 Tom Tromey New
[v3,05/15] arm: Add support for VPR_REG in arm_class_likely_spilled_p ARM/MVE use vectors of boolean for predicates - - - - --- 2022-01-13 Christophe Lyon New
[v3,05/12] x86: Update piecewise move and store [v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE - - - - --- 2021-05-17 H.J. Lu New
[v3,05/12] arm: vst1_types_x3 ACLE intrinsics arm: vld1q vst1 vst1q vst1 intrinsics - - - - --- 2024-01-02 Ezra Sitorus New
[v3,05/12] Rename section and encoding functions from i386 which will be used in aarch64 Add aarch64-w64-mingw32 target - - - - --- 2024-04-11 Evgeny Karpov New
[v3,05/12] LoongArch Port: Builtin functions. Add LoongArch support. - - - - --- 2021-12-10 Chenghua Xu New
[v3,05/11] riscv: thead: Add support for the XTheadBb ISA extension RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,05/11] c: Turn int-conversion warnings into permerrors : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,05/11] OpenMP: push attaches to end of clause list in "target" regions OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,05/10] testsuite: Add check for unsupported TI ABI PRU features to testsuite New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,05/10] RISCV: Strengthen atomic stores RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,05/10] GCN back-end code AMD GCN Port v3 - - - - --- 2018-12-12 Andrew Stubbs New
[v3,04/18] add configury - - - - --- 2013-08-20 Tom Tromey New
[v3,04/15] arm: Add GENERAL_AND_VPR_REGS regclass ARM/MVE use vectors of boolean for predicates - - - - --- 2022-01-13 Christophe Lyon New
[v3,04/12] arm: vst1_types_x2 ACLE intrinsics arm: vld1q vst1 vst1q vst1 intrinsics - - - - --- 2024-01-02 Ezra Sitorus New
[v3,04/12] Reuse MinGW from i386 for AArch64 Add aarch64-w64-mingw32 target - - - - --- 2024-04-11 Evgeny Karpov New
[v3,04/12] Remove MAX_BITSIZE_MODE_ANY_INT [v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE - - - - --- 2021-05-17 H.J. Lu New
[v3,04/12] LoongArch Port: Machine description C files and .h files. Add LoongArch support. - - - - --- 2021-12-10 Chenghua Xu New
[v3,04/11] riscv: thead: Add support for the XTheadBs ISA extension RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,04/11] OpenMP/OpenACC: mapping group list-handling improvements OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,04/11] Add tests for validating future C permerrors : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,04/10] testsuite: Add check for overflowed IMEM region to testsuite New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,04/10] RISCV: Add AMO release bits RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,04/10] GCN machine description AMD GCN Port v3 - - - - --- 2018-12-12 Andrew Stubbs New
[v3,03/18] move generated_files order-only dependency later - - - - --- 2013-08-20 Tom Tromey New
[v3,03/15] arm: Add tests for PR target/101325 ARM/MVE use vectors of boolean for predicates - - - - --- 2022-01-13 Christophe Lyon New
[v3,03/12] x86: Avoid stack realignment when copying data [v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE - - - - --- 2021-05-17 H.J. Lu New
[v3,03/12] arm: vld1q_types_x4 ACLE intrinsics arm: vld1q vst1 vst1q vst1 intrinsics - - - - --- 2024-01-02 Ezra Sitorus New
[v3,03/12] aarch64: Add aarch64-w64-mingw32 COFF Add aarch64-w64-mingw32 target - - - - --- 2024-04-11 Evgeny Karpov New
[v3,03/12] LoongArch Port: Machine Decsription files. Add LoongArch support. - - - - --- 2021-12-10 Chenghua Xu New
[v3,03/11] riscv: thead: Add support for the XTheadBa ISA extension RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,03/11] gm2: Add missing declaration of m2pim_M2RTS_Terminate to test : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,03/11] OpenMP/OpenACC struct sibling list gimplification extension and rework OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,03/10] testsuite: Add PRU tests New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,03/10] RISCV: Enforce atomic compare_exchange SEQ_CST RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,03/10] GCN libgcc. AMD GCN Port v3 - - - - --- 2018-12-12 Andrew Stubbs New
[v3,02/18] update generated_files - - - - --- 2013-08-20 Tom Tromey New
[v3,02/15] arm: Add tests for PR target/100757 ARM/MVE use vectors of boolean for predicates - - - - --- 2022-01-13 Christophe Lyon New
[v3,02/12] x86: Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE [v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE - - - - --- 2021-05-17 H.J. Lu New
[v3,02/12] arm: vld1q_types_x3 ACLE intrinsics arm: vld1q vst1 vst1q vst1 intrinsics - - - - --- 2024-01-02 Ezra Sitorus New
[v3,02/12] aarch64: Mark x18 register as a fixed register for MS ABI Add aarch64-w64-mingw32 target - - - - --- 2024-04-11 Evgeny Karpov New
[v3,02/12] LoongArch Port: Regenerate gcc/configure. Add LoongArch support. - - - - --- 2021-12-10 Chenghua Xu New
[v3,02/11] riscv: riscv-cores.def: Add T-Head XuanTie C906 RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,02/11] aarch64: Call named function in gcc.target/aarch64/aapcs64/ice_1.c : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,02/11] Remove omp_target_reorder_clauses OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,02/10] Initial TI PRU libgcc port New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,02/10] GCN libgfortran. AMD GCN Port v3 - - - - --- 2018-12-12 Andrew Stubbs New
[v3,01/31] PR target/58901: reload: Handle SUBREG of MEM with a mode-dependent address [v3,01/31] PR target/58901: reload: Handle SUBREG of MEM with a mode-dependent address - - - - --- 2020-11-27 Maciej W. Rozycki Accepted
[v3,01/18] clean up SHLIB so subshells are not needed - - - - --- 2013-08-20 Tom Tromey New
[v3,01/15] arm: Add new tests for comparison vectorization with Neon and MVE ARM/MVE use vectors of boolean for predicates - - - - --- 2022-01-13 Christophe Lyon New
[v3,01/12] arm: vld1q_types_x2 ACLE intrinsics arm: vld1q vst1 vst1q vst1 intrinsics - - - - --- 2024-01-02 Ezra Sitorus New
[v3,01/12] LoongArch Port: gcc build Add LoongArch support. - - - - --- 2021-12-10 Chenghua Xu New
[v3,01/12] Introduce aarch64-w64-mingw32 target Add aarch64-w64-mingw32 target - - - - --- 2024-04-11 Evgeny Karpov New
[v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE [v3,01/12] Add TARGET_READ_MEMSET_VALUE/TARGET_GEN_MEMSET_VALUE - - - - --- 2021-05-17 H.J. Lu New
[v3,01/11] riscv: Add basic XThead* vendor extension support RISC-V: Add XThead* extension support - - - - --- 2023-02-24 Christoph Müllner New
[v3,01/11] aarch64: Avoid -Wincompatible-pointer-types warning in Linux unwinder : More warnings as errors by default - - - - --- 2023-11-20 Florian Weimer New
[v3,01/11] OpenMP 5.0: Clause ordering for OpenMP 5.0 (topological sorting by base pointer) OpenMP 5.0: Struct & mapping clause expansion rework - - - - --- 2022-09-13 Julian Brown New
[v3,01/10] RISCV: Eliminate SYNC memory models RISCV: Implement ISA Manual Table A.6 Mappings - - - - --- 2023-04-10 Patrick O'Neill New
[v3,01/10] Initial TI PRU GCC port New backend for the TI PRU processor - - - - --- 2018-08-16 Dimitar Dimitrov New
[v3,00/10] MIPS vectorization improvements - - - - --- 2011-12-23 Richard Henderson New
[v2] xtensa: implement trap pattern - - - - --- 2015-06-09 Max Filippov New
[v2] xtensa: Prepare the transition from Reload to LRA [v2] xtensa: Prepare the transition from Reload to LRA - - - - --- 2022-10-18 Takayuki 'January June' Suwa New
[v2] xtensa: Optimize stack frame adjustment more [v2] xtensa: Optimize stack frame adjustment more - - - - --- 2023-01-07 Takayuki 'January June' Suwa New
[v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode [v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode - - - - --- 2023-06-05 Takayuki 'January June' Suwa New
[v2] xtensa: Optimize bitwise splicing operation [v2] xtensa: Optimize bitwise splicing operation - - - - --- 2023-01-08 Takayuki 'January June' Suwa New
[v2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' [v2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0' - - - - --- 2023-05-23 Takayuki 'January June' Suwa New
[v2] xtensa: Make register A0 allocable for the CALL0 ABI [v2] xtensa: Make register A0 allocable for the CALL0 ABI - - - - --- 2022-10-21 Takayuki 'January June' Suwa New
[v2] xtensa: Make full transition to LRA [v2] xtensa: Make full transition to LRA - - - - --- 2023-05-08 Takayuki 'January June' Suwa New
[v2] xtensa: Make full transition to LRA [v2] xtensa: Make full transition to LRA - - - - --- 2024-01-24 Max Filippov New
[v2] xtensa: Eliminate unnecessary general-purpose reg-reg moves [v2] xtensa: Eliminate unnecessary general-purpose reg-reg moves - - - - --- 2023-01-18 Takayuki 'January June' Suwa New
[v2] xtensa: Eliminate the use of callee-saved register that saves and restores only once [v2] xtensa: Eliminate the use of callee-saved register that saves and restores only once - - - - --- 2023-01-17 Takayuki 'January June' Suwa New
[v2] xfail fetestexcept test - ppc always uses fcmpu [v2] xfail fetestexcept test - ppc always uses fcmpu - - - - --- 2024-04-22 Alexandre Oliva New
[v2] x86_64: Some SUBREG related optimization tweaks to i386 backend. [v2] x86_64: Some SUBREG related optimization tweaks to i386 backend. - - - - --- 2021-10-13 Roger Sayle New
[v2] x86: {,v}psadbw have commutative source operands [v2] x86: {,v}psadbw have commutative source operands - - - - --- 2022-06-02 Jan Beulich New
[v2] x86: set spincount 1 for x86 hybrid platform [v2] x86: set spincount 1 for x86 hybrid platform - - - - --- 2023-10-11 Jun Zhang New
[v2] x86: make better use of VBROADCASTSS / VPBROADCASTD [v2] x86: make better use of VBROADCASTSS / VPBROADCASTD - - - - --- 2023-06-21 Jan Beulich New
[v2] x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F [v2] x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F - - - - --- 2023-06-16 Jan Beulich New
[v2] x86: correct and improve "*vec_dupv2di" [v2] x86: correct and improve "*vec_dupv2di" - - - - --- 2023-06-16 Jan Beulich New
[v2] x86: allow to suppress default clobbers added to asm()s - - - - --- 2016-07-06 Jan Beulich New
[v2] x86: Warn for excessive argument alignment in main [v2] x86: Warn for excessive argument alignment in main - - - - --- 2021-05-17 H.J. Lu New
[v2] x86: Support x32 and IBT in heap trampoline [v2] x86: Support x32 and IBT in heap trampoline - - - - --- 2024-02-13 H.J. Lu New
[v2] x86: Save callee-saved registers in noreturn functions for -O0/-Og [v2] x86: Save callee-saved registers in noreturn functions for -O0/-Og - - - - --- 2024-01-27 H.J. Lu New
[v2] x86: Remove "%!" before ret [v2] x86: Remove "%!" before ret - - - - --- 2021-11-17 H.J. Lu New
[v2] x86: Properly find the maximum stack slot alignment [v2] x86: Properly find the maximum stack slot alignment - - - - --- 2023-07-07 H.J. Lu New
[v2] x86: Properly disable -fsplit-stack support on non-glibc targets [v2] x86: Properly disable -fsplit-stack support on non-glibc targets - - - - --- 2022-01-21 H.J. Lu New
[v2] x86: Optimize load of const all 1s float vectors [v2] x86: Optimize load of const all 1s float vectors - - - - --- 2021-08-09 H.J. Lu New
[v2] x86: Issue error for return/argument only with function body [v2] x86: Issue error for return/argument only with function body - - - - --- 2021-03-19 H.J. Lu New
[v2] x86: Generate REG_CFA_UNDEFINED for unsaved callee-saved registers [v2] x86: Generate REG_CFA_UNDEFINED for unsaved callee-saved registers - - - - --- 2024-01-29 H.J. Lu New
[v2] x86: Fix -fsplit-stack feature detection via TARGET_CAN_SPLIT_STACK [v2] x86: Fix -fsplit-stack feature detection via TARGET_CAN_SPLIT_STACK - - - - --- 2022-02-21 Li, Pan2 via Gcc-patches New
[v2] x86: Enable FMA in unsigned SI to SF expanders [v2] x86: Enable FMA in unsigned SI to SF expanders - - - - --- 2021-09-06 H.J. Lu New
[v2] x86: Don't set AVX_U128_DIRTY when all bits are zero [v2] x86: Don't set AVX_U128_DIRTY when all bits are zero - - - - --- 2021-07-16 H.J. Lu New
[v2] x86: Don't return hard register when LRA is in progress [v2] x86: Don't return hard register when LRA is in progress - - - - --- 2021-07-23 H.J. Lu New
[v2] x86: Don't enable UINTR in 32-bit mode [v2] x86: Don't enable UINTR in 32-bit mode - - - - --- 2021-07-13 H.J. Lu New
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