Patchwork GNU Compiler Collection

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Patch A/R/T Date Submitter Delegate State
[AArch64] Fix possible wrong code generation when comparing DImode values. 0 0 0 2014-02-24 James Greenhalgh New
[AArch64] Fix parameters to vcvtx_high 0 0 0 2013-09-06 James Greenhalgh New
[AArch64] Fix over length lines around aarch64_save_or_restore_fprs 0 0 0 2013-11-20 Marcus Shawcroft New
[AArch64] Fix output template for Scalar Neon->Neon register move. 0 0 0 2013-10-16 James Greenhalgh New
[AArch64] Fix order of modes to lroundmn2 standard names. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Fix offset glitch in load reg pair pattern 0 0 0 2014-07-29 Jiong Wang New
[AArch64] Fix name of macros called in the vdup_lane Neon intrinsics 0 0 0 2013-08-12 James Greenhalgh New
[AArch64] Fix macro in vdup_lane_2 test case 0 0 0 2014-05-08 Ian Bolton New
[AArch64] Fix invalid assembler in scalar_intrinsics.c test 0 0 0 2013-05-22 Ian Bolton New
[AArch64] Fix integer vabs intrinsics 0 0 0 2014-05-02 James Greenhalgh New
[AArch64] Fix for PR62040 0 0 0 2014-08-20 Carrot Wei New
[AArch64] Fix for PR62040 0 0 0 2014-09-04 Carrot Wei New
[AArch64] Fix for LDR/STR to/from S and D registers 0 0 0 2013-05-01 Ian Bolton New
[AArch64] Fix faulty commit of testsuite/gcc.target/aarch64/csinc-2.c 0 0 0 2012-11-16 Ian Bolton New
[AArch64] Fix early-clobber operands to vtbx[1,3] 0 0 0 2013-10-11 James Greenhalgh New
[AArch64] Fix early-clobber operands to vtbx[1,3] 0 0 0 2013-10-12 James Greenhalgh New
[AArch64] Fix duplication in test case. 0 0 0 2013-04-03 Tejas Belagod New
[AArch64] Fix default CPU configurations 0 0 0 2014-02-25 Kyrylo Tkachov New
[AArch64] Fix configure test for AArch64 dwarf2 debug_line 0 0 0 2013-08-22 Julian Brown New
[AArch64] Fix configure test for AArch64 dwarf2 debug_line 0 0 0 2013-08-22 Paolo Carlini New
[AArch64] Fix categorisation of the frecp* insns. 0 0 0 2013-09-03 James Greenhalgh New
[AArch64] Fix behaviour of -mcpu option to match ARM. 0 0 0 2014-01-16 James Greenhalgh New
[AArch64] Fix argument types for some high_lane* intrinsics implemented in assembly 0 0 0 2014-07-09 Kyrylo Tkachov New
[AArch64] Fix aarch64_simd_valid_immediate for Bigendian 0 0 0 2014-03-21 Alan Lawrence New
[AArch64] Fix REG_CFA_RESTORE mode. 0 0 0 2014-06-10 Marcus Shawcroft New
[AArch64] Fix PR63293 0 0 0 2014-09-19 Jiong Wang New
[AArch64] Fix PR63293 0 0 0 2014-09-25 Jiong Wang New
[AArch64] Fix Narrowing high shifts. 0 0 0 2012-09-10 Tejas Belagod New
[AArch64] FP vdiv tescase made big-endian safe 0 0 0 2013-11-19 Alex Velenko New
[AArch64] Expand binary operations' constant operands for neon intrinsics. 0 0 0 2012-09-10 Tejas Belagod New
[AArch64] Enable shuffle on big-endian and turn on the testsuite 0 0 0 2014-04-11 Alan Lawrence New
[AArch64] Enable shrink wrap 0 0 0 2014-09-04 Jiong Wang New
[AArch64] Enable Redundant Extension Elimination by default at 02 or higher 0 0 0 2013-04-24 Ian Bolton New
[AArch64] Enable Address sanitizer and UB sanitizer 0 0 0 2014-09-05 Christophe Lyon New
[AArch64] Enable Address sanitizer and UB sanitizer 0 0 0 2014-09-26 Andreas Schwab New
[AArch64] Describe the 'BSL' RTL pattern more accurately. 0 0 0 2013-04-25 James Greenhalgh New
[AArch64] Define vec_extract. 0 0 0 2013-11-05 Tejas Belagod New
[AArch64] Define __ARM_NEON by default 0 0 0 2014-02-24 Ian Bolton New
[AArch64] Define TARGET_FLAGS_REGNUM 0 0 0 2014-02-28 Ramana Radhakrishnan New
[AArch64] Define BE loader name. 0 0 0 2014-01-06 Marcus Shawcroft New
[AArch64] Correct cache line size calculation 0 0 0 2012-09-03 Marcus Shawcroft New
[AArch64] Convert ld1, st1 arm_neon.h intrinsics to RTL builtins. 0 0 0 2013-07-02 James Greenhalgh New
[AArch64] Convert ld1, st1 arm_neon.h intrinsics to RTL builtins. 0 0 0 2013-07-04 James Greenhalgh New
[AArch64] Convert NEON frint implementations to use builtins. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Compare instruction in shift_extend mode 0 0 0 2013-04-12 Hurugalawadi, Naveen New
[AArch64] Compare instruction in shift_extend mode 0 0 0 2013-04-15 Hurugalawadi, Naveen New
[AArch64] Compare instruction in shift_extend mode 0 0 0 2013-04-17 Hurugalawadi, Naveen New
[AArch64] Compare Negative instruction in shift and extend mode 0 0 0 2013-04-10 Hurugalawadi, Naveen New
[AArch64] Classify FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM as POINTER_REGS. 0 0 0 2013-10-16 Marcus Shawcroft New
[AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32} 0 0 0 2014-09-11 James Greenhalgh New
[AArch64] Change to pass -mabi=* directly to the assembler 0 0 0 2013-07-19 Yufeng Zhang New
[AArch64] Change iterator for neg<mode>2 from VDQM to VDQ. 0 0 0 2013-04-25 James Greenhalgh New
[AArch64] Bitwise adds and subs instructions with shift 0 0 0 2013-03-26 Hurugalawadi, Naveen New
[AArch64] Bitwise adds and subs instructions with shift 0 0 0 2013-04-02 Hurugalawadi, Naveen New
[AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c 0 0 0 2014-09-18 James Greenhalgh New
[AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c 0 0 0 2014-09-22 James Greenhalgh New
[AArch64] Allow symbol+offset even if not being used for memory access 0 0 0 2012-08-31 Ian Bolton New
[AArch64] Allow symbol+offset even if not being used for memory access 0 0 0 2012-09-10 Richard Henderson New
[AArch64] Allow symbol+offset as symbolic constant expression 0 0 0 2012-07-06 Ian Bolton New
[AArch64] Allow insv_imm to handle bigger immediates via masking to 16-bits 0 0 0 2013-05-17 Ian Bolton New
[AArch64] Adjust preferred_reload_class of SP+C 0 0 0 2013-10-17 Marcus Shawcroft New
[AArch64] Adjust gcc.dg/torture/stackalign/builtin-apply-2.c 0 0 0 2013-06-17 Yufeng Zhang New
[AArch64] Add/Sub and set flags instructions in extend and shift_extend mode 0 0 0 2013-04-12 Hurugalawadi, Naveen New
[AArch64] Add/Sub and set flags instructions in extend and shift_extend mode 0 0 0 2013-04-15 Hurugalawadi, Naveen New
[AArch64] Add zip{1, 2}, uzp{1, 2}, trn{1, 2} support for vector permute. 0 0 0 2012-12-04 James Greenhalgh New
[AArch64] Add w -> w constraint to vec_set. 0 0 0 2013-11-05 Tejas Belagod New
[AArch64] Add vector int to float conversions. 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Add vector fix, fixuns, fix_trunc, fixuns_trunc standard patterns 0 0 0 2013-04-26 James Greenhalgh New
[AArch64] Add vcond, vcondu support. 0 0 0 2012-10-09 James Greenhalgh New
[AArch64] Add vabs_s64 intrinsic 0 0 0 2013-07-12 Ian Bolton New
[AArch64] Add vabs_s64 intrinsic 0 0 0 2013-07-19 Ian Bolton New
[AArch64] Add testcases to cover various pro/epi stack layout 0 0 0 2014-06-10 Jiong Wang New
[AArch64] Add testcases for FAC, FCM changes. 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Add support for vectorizable standard math patterns. 0 0 0 2012-11-27 James Greenhalgh New
[AArch64] Add support for floating-point vcond. 0 0 0 2013-01-08 James Greenhalgh New
[AArch64] Add support for crtfastmath.c 0 0 0 2014-09-05 Ramana Radhakrishnan New
[AArch64] Add support for TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES hook. 0 0 0 2012-12-06 James Greenhalgh New
[AArch64] Add support for TARGET_BUILTIN_DECL 0 0 0 2012-11-21 James Greenhalgh New
[AArch64] Add support for "wsp" register 0 0 0 2013-07-04 Yufeng Zhang New
[AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}. 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Add secondary reload for immediates into FP_REGS 0 0 0 2013-07-30 Ian Bolton New
[AArch64] Add predicate for storewb_pair/loadwb_pair 0 0 0 2014-06-12 Jiong Wang New
[AArch64] Add missing copyright and build dependency for aarch64-simd-builtins.def 0 0 0 2013-02-22 James Greenhalgh New
[AArch64] Add handling of bswap operations in rtx costs 0 0 0 2014-03-19 Kyrylo Tkachov New
[AArch64] Add constrain to address offset in storewb_pair/loadwb_pair insns 0 0 0 2014-07-29 Jiong Wang New
[AArch64] Add combiner patterns for FAC instructions 0 0 0 2013-04-30 James Greenhalgh New
[AArch64] Add basic recognition for cpu cortex-a53 and cortex-a57 0 0 0 2012-12-14 Yufeng Zhang New
[AArch64] Add a builtin for rbit(q?)_p8; add intrinsics and tests. 0 0 0 2014-08-19 Alan Lawrence New
[AArch64] Add a big-endian lane flip at expand-time in saturating math patterns 0 0 0 2014-06-10 Kyrylo Tkachov New
[AArch64] Add --enable-fix-cortex-a53-835769 configure-time option 0 0 0 2014-10-10 Kyrylo Tkachov New
[AArch64] AND operation should use CC_NZ mode 0 0 0 2013-02-01 Ian Bolton New
[AArch64] AArch64 SIMD Builtins Better Type Correctness. 0 0 0 2013-11-18 James Greenhalgh New
[AArch64] : Fix test harness to for unaligned vector mem access. 0 0 0 2012-12-19 Tejas Belagod New
[AArch64] : Fix format of <su>mull<q> instruction. 0 0 0 2013-01-08 Tejas Belagod New
[AArch64] : Add constraint letter for stack_protect_test pattern. 0 0 0 2014-09-04 Venkataramanan Kumar New
[AArch64] : Add constraint letter for stack_protect_test pattern) 0 0 0 2014-09-17 James Greenhalgh New
[AArch64] : Add constraint letter for stack_protect_test pattern) 0 0 0 2014-09-18 James Greenhalgh New
[AArch64] 64-bit float vreinterpret implemention 0 0 0 2014-02-25 Alex Velenko New
[AArch64] 64-bit float vreinterpret implemention 0 0 0 2014-02-28 Alex Velenko New
[AArch64] -mcmodel=tiny -fPIC use tiny absolute for non binds local. 0 0 0 2013-05-31 Marcus Shawcroft New