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Tue, 09 Jan 2024 17:32:02 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Date: Tue, 9 Jan 2024 17:31:55 -0800 Message-Id: <20240110013159.2645757-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This series is a prototype for adding all typed instructions to a dfa scheduling pipeline. This is what I currently have for cleaning up the cost models. Adding the vector insns to the dfa pipelines changes the expected output of a lot of test cases as expected. Should I update the expected output of the test cases to the output of the new cost model? I'm not fully sure which codegen is more optimal. Please let me know if I should do so and I'll add a patch adjusting the expected testcase output. Edwin Lu (4): RISC-V: Add non-vector types to dfa pipelines RISC-V: Add vector related reservations RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 RISC-V: Enable assert for insn_has_dfa_reservation --- V2: - Update non-vector insn types and add new pipelines - Add -fno-schedule-insn -fno-schedule-insn2 to some test cases --- gcc/config/riscv/generic-ooo.md | 40 ++++- gcc/config/riscv/generic.md | 163 +++++++++++++++++- gcc/config/riscv/riscv.cc | 6 +- gcc/config/riscv/riscv.md | 18 +- gcc/config/riscv/sifive-7.md | 161 ++++++++++++++++- gcc/config/riscv/vector.md | 2 +- gcc/config/riscv/zc.md | 96 +++++------ .../g++.target/riscv/rvv/base/bug-1.C | 2 + .../riscv/rvv/autovec/reduc/reduc_call-2.c | 2 + .../riscv/rvv/base/binop_vx_constraint-102.c | 2 + .../riscv/rvv/base/binop_vx_constraint-108.c | 2 + .../riscv/rvv/base/binop_vx_constraint-114.c | 2 + .../riscv/rvv/base/binop_vx_constraint-119.c | 2 + .../riscv/rvv/base/binop_vx_constraint-12.c | 2 + .../riscv/rvv/base/binop_vx_constraint-16.c | 2 + .../riscv/rvv/base/binop_vx_constraint-17.c | 2 + .../riscv/rvv/base/binop_vx_constraint-19.c | 2 + .../riscv/rvv/base/binop_vx_constraint-21.c | 2 + .../riscv/rvv/base/binop_vx_constraint-23.c | 2 + .../riscv/rvv/base/binop_vx_constraint-25.c | 2 + .../riscv/rvv/base/binop_vx_constraint-27.c | 2 + .../riscv/rvv/base/binop_vx_constraint-29.c | 2 + .../riscv/rvv/base/binop_vx_constraint-31.c | 2 + .../riscv/rvv/base/binop_vx_constraint-33.c | 2 + .../riscv/rvv/base/binop_vx_constraint-35.c | 2 + .../riscv/rvv/base/binop_vx_constraint-4.c | 2 + .../riscv/rvv/base/binop_vx_constraint-40.c | 2 + .../riscv/rvv/base/binop_vx_constraint-44.c | 2 + .../riscv/rvv/base/binop_vx_constraint-50.c | 2 + .../riscv/rvv/base/binop_vx_constraint-56.c | 2 + .../riscv/rvv/base/binop_vx_constraint-62.c | 2 + .../riscv/rvv/base/binop_vx_constraint-68.c | 2 + .../riscv/rvv/base/binop_vx_constraint-74.c | 2 + .../riscv/rvv/base/binop_vx_constraint-79.c | 2 + .../riscv/rvv/base/binop_vx_constraint-8.c | 2 + .../riscv/rvv/base/binop_vx_constraint-84.c | 2 + .../riscv/rvv/base/binop_vx_constraint-90.c | 2 + .../riscv/rvv/base/binop_vx_constraint-96.c | 2 + .../rvv/base/float-point-dynamic-frm-30.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-1.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-2.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-3.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-7.c | 2 + .../riscv/rvv/base/shift_vx_constraint-1.c | 2 + .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 + gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 + 65 files changed, 532 insertions(+), 70 deletions(-)