mbox series

[v4,0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

Message ID 20231212193253.220195-1-mary.bennett@embecosm.com
Headers show
Series RISC-V: Support CORE-V XCVELW and XCVBI extensions | expand

Message

Mary Bennett Dec. 12, 2023, 7:32 p.m. UTC 
Thank you for reviewing my patches!

v1 -> v2:
  * Bring the MEM into the operand for cv.elw. The new predicate is
    move_operand.
  * Add comment to riscv.md detailing why corev.md must appear before
    the generic riscv instructions.

v2 -> v3:
  * Merge patterns for CORE-V branch immediate and generic RISC-V so to
    supress the generic patterns if XCVbi is available.

v3 -> v4:
  * Add duplicate content of "*branch<mode>" to corev.md.

This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc       |  4 ++
 gcc/config/riscv/constraints.md               | 21 +++++---
 gcc/config/riscv/corev.def                    |  3 ++
 gcc/config/riscv/corev.md                     | 51 ++++++++++++++++++-
 gcc/config/riscv/predicates.md                |  4 ++
 gcc/config/riscv/riscv-builtins.cc            |  2 +
 gcc/config/riscv/riscv-ftypes.def             |  1 +
 gcc/config/riscv/riscv.md                     |  2 +-
 gcc/config/riscv/riscv.opt                    |  4 ++
 gcc/doc/extend.texi                           |  8 +++
 gcc/doc/sourcebuild.texi                      |  6 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 ++++
 gcc/testsuite/lib/target-supports.exp         | 26 ++++++++++
 17 files changed, 263 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c