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[0/1] RISC-V: Support CORE-V XCVMEM extension

Message ID 20231109124219.966619-1-mary.bennett@embecosm.com
Headers show
Series RISC-V: Support CORE-V XCVMEM extension | expand

Message

Mary Bennett Nov. 9, 2023, 12:42 p.m. UTC 
This patch series presents the comprehensive implementation of the MEM
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

RISC-V: Add support for XCVmem extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc       |   2 +
 gcc/config/riscv/constraints.md               |  28 +++
 gcc/config/riscv/corev.md                     | 227 ++++++++++++++++++
 gcc/config/riscv/predicates.md                |  20 +-
 gcc/config/riscv/riscv-protos.h               |  12 +-
 gcc/config/riscv/riscv.cc                     |  48 +++-
 gcc/config/riscv/riscv.h                      |   6 +-
 gcc/config/riscv/riscv.md                     |  46 ++--
 gcc/config/riscv/riscv.opt                    |   2 +
 gcc/doc/sourcebuild.texi                      |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c    |  23 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c    |  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c    |  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c    |  23 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c    |  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c    |  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c    |  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c    |  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c    |  22 ++
 .../riscv/cv-mem-operand-compile-1.c          |  19 ++
 .../riscv/cv-mem-operand-compile-2.c          |  20 ++
 .../riscv/cv-mem-operand-compile-3.c          |  28 +++
 .../riscv/cv-mem-operand-compile-4.c          |  21 ++
 .../riscv/cv-mem-operand-compile-5.c          |  25 ++
 .../riscv/cv-mem-operand-compile-6.c          |  21 ++
 .../riscv/cv-mem-operand-compile-7.c          |  24 ++
 .../riscv/cv-mem-operand-compile-8.c          |  18 ++
 .../gcc.target/riscv/cv-mem-sb-compile-1.c    |  36 +++
 .../gcc.target/riscv/cv-mem-sb-compile-2.c    |  38 +++
 .../gcc.target/riscv/cv-mem-sb-compile-3.c    |  30 +++
 .../gcc.target/riscv/cv-mem-sh-compile-1.c    |  36 +++
 .../gcc.target/riscv/cv-mem-sh-compile-2.c    |  38 +++
 .../gcc.target/riscv/cv-mem-sh-compile-3.c    |  30 +++
 .../gcc.target/riscv/cv-mem-sw-compile-1.c    |  36 +++
 .../gcc.target/riscv/cv-mem-sw-compile-2.c    |  38 +++
 .../gcc.target/riscv/cv-mem-sw-compile-3.c    |  30 +++
 gcc/testsuite/lib/target-supports.exp         |  14 ++
 43 files changed, 1216 insertions(+), 30 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c