[0/3,i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512

Message ID	20210804123928.90586-1-hongtao.liu@intel.com
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0913838515E0 To: gcc-patches@gcc.gnu.org Subject: [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 Date: Wed, 4 Aug 2021 20:39:25 +0800 Message-Id: <20210804123928.90586-1-hongtao.liu@intel.com> Precedence: list From: liuhongt via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: liuhongt <hongtao.liu@intel.com> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>
Series	Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 \| expand [0/3,i386] Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 [1/3,i386] Support cond_{smax, smin, umax, umin} for vector integer modes under AVX512. [2/3,i386] Support cond_{smax, smin} for vector float/double modes under AVX512. [3/3,i386] Support cond_{xor, ior, and} for vector integer mode under AVX512.

Message ID

20210804123928.90586-1-hongtao.liu@intel.com

Headers

DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0913838515E0
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 0/3] [i386] Support cond_{smax, smin, umax, umin, xor, ior,
 and} for vector modes under AVX512
Date: Wed,  4 Aug 2021 20:39:25 +0800
Message-Id: <20210804123928.90586-1-hongtao.liu@intel.com>
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Reply-To: liuhongt <hongtao.liu@intel.com>
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Series

Support cond_{smax, smin, umax, umin, xor, ior, and} for vector modes under AVX512 | expand

Message

liuhongt Aug. 4, 2021, 12:39 p.m. UTC

Hi:
  Together with the previous 3 patches, all cond_op expanders of vector
modes are supported (if they have a corresponding avx512 mask instruction).

  Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
  
liuhongt (3):
  [i386] Support cond_{smax,smin,umax,umin} for vector integer modes
    under AVX512.
  [i386] Support cond_{smax,smin} for vector float/double modes under
    AVX512.
  [i386] Support cond_{xor,ior,and} for vector integer mode under
    AVX512.

 gcc/config/i386/sse.md                        | 54 +++++++++++++
 .../gcc.target/i386/cond_op_anylogic_d-1.c    | 38 +++++++++
 .../gcc.target/i386/cond_op_anylogic_d-2.c    | 78 +++++++++++++++++++
 .../gcc.target/i386/cond_op_anylogic_q-1.c    | 10 +++
 .../gcc.target/i386/cond_op_anylogic_q-2.c    |  5 ++
 .../gcc.target/i386/cond_op_maxmin_b-1.c      |  8 ++
 .../gcc.target/i386/cond_op_maxmin_b-2.c      |  6 ++
 .../gcc.target/i386/cond_op_maxmin_d-1.c      | 41 ++++++++++
 .../gcc.target/i386/cond_op_maxmin_d-2.c      | 67 ++++++++++++++++
 .../gcc.target/i386/cond_op_maxmin_double-1.c | 39 ++++++++++
 .../gcc.target/i386/cond_op_maxmin_double-2.c | 67 ++++++++++++++++
 .../gcc.target/i386/cond_op_maxmin_float-1.c  |  8 ++
 .../gcc.target/i386/cond_op_maxmin_float-2.c  |  5 ++
 .../gcc.target/i386/cond_op_maxmin_q-1.c      |  8 ++
 .../gcc.target/i386/cond_op_maxmin_q-2.c      |  5 ++
 .../gcc.target/i386/cond_op_maxmin_ub-1.c     |  8 ++
 .../gcc.target/i386/cond_op_maxmin_ub-2.c     |  6 ++
 .../gcc.target/i386/cond_op_maxmin_ud-1.c     |  8 ++
 .../gcc.target/i386/cond_op_maxmin_ud-2.c     |  5 ++
 .../gcc.target/i386/cond_op_maxmin_uq-1.c     |  8 ++
 .../gcc.target/i386/cond_op_maxmin_uq-2.c     |  5 ++
 .../gcc.target/i386/cond_op_maxmin_uw-1.c     |  8 ++
 .../gcc.target/i386/cond_op_maxmin_uw-2.c     |  6 ++
 .../gcc.target/i386/cond_op_maxmin_w-1.c      |  8 ++
 .../gcc.target/i386/cond_op_maxmin_w-2.c      |  6 ++
 25 files changed, 507 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c

Comments

Hongtao Liu Aug. 4, 2021, 12:48 p.m. UTC | #1

On Wed, Aug 4, 2021 at 8:39 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
>   Together with the previous 3 patches, all cond_op expanders of vector
> modes are supported (if they have a corresponding avx512 mask instruction).
Oh, after double check, I realize there're still shift instructions
left, will support in another patch,
OPTAB_D (cond_ashl_optab, "cond_ashl$a")
OPTAB_D (cond_ashr_optab, "cond_ashr$a")
OPTAB_D (cond_lshr_optab, "cond_lshr$a")
>
>   Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
>
> liuhongt (3):
>   [i386] Support cond_{smax,smin,umax,umin} for vector integer modes
>     under AVX512.
>   [i386] Support cond_{smax,smin} for vector float/double modes under
>     AVX512.
>   [i386] Support cond_{xor,ior,and} for vector integer mode under
>     AVX512.
>
>  gcc/config/i386/sse.md                        | 54 +++++++++++++
>  .../gcc.target/i386/cond_op_anylogic_d-1.c    | 38 +++++++++
>  .../gcc.target/i386/cond_op_anylogic_d-2.c    | 78 +++++++++++++++++++
>  .../gcc.target/i386/cond_op_anylogic_q-1.c    | 10 +++
>  .../gcc.target/i386/cond_op_anylogic_q-2.c    |  5 ++
>  .../gcc.target/i386/cond_op_maxmin_b-1.c      |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_b-2.c      |  6 ++
>  .../gcc.target/i386/cond_op_maxmin_d-1.c      | 41 ++++++++++
>  .../gcc.target/i386/cond_op_maxmin_d-2.c      | 67 ++++++++++++++++
>  .../gcc.target/i386/cond_op_maxmin_double-1.c | 39 ++++++++++
>  .../gcc.target/i386/cond_op_maxmin_double-2.c | 67 ++++++++++++++++
>  .../gcc.target/i386/cond_op_maxmin_float-1.c  |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_float-2.c  |  5 ++
>  .../gcc.target/i386/cond_op_maxmin_q-1.c      |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_q-2.c      |  5 ++
>  .../gcc.target/i386/cond_op_maxmin_ub-1.c     |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_ub-2.c     |  6 ++
>  .../gcc.target/i386/cond_op_maxmin_ud-1.c     |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_ud-2.c     |  5 ++
>  .../gcc.target/i386/cond_op_maxmin_uq-1.c     |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_uq-2.c     |  5 ++
>  .../gcc.target/i386/cond_op_maxmin_uw-1.c     |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_uw-2.c     |  6 ++
>  .../gcc.target/i386/cond_op_maxmin_w-1.c      |  8 ++
>  .../gcc.target/i386/cond_op_maxmin_w-2.c      |  6 ++
>  25 files changed, 507 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_d-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_anylogic_q-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_b-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_d-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_double-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_float-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_q-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ub-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_ud-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uq-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_uw-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cond_op_maxmin_w-2.c
>
> --
> 2.18.1
>