diff mbox series

[V2] mtrr: add tests for enable bits in MTRR_DEF_TYPE MSR

Message ID 20201117194324.600426-2-alex.hung@canonical.com
State Accepted
Headers show
Series [V2] mtrr: add tests for enable bits in MTRR_DEF_TYPE MSR | expand

Commit Message

Alex Hung Nov. 17, 2020, 7:43 p.m. UTC 
Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/bios/mtrr/mtrr.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Comments

Colin Ian King Nov. 17, 2020, 7:46 p.m. UTC | #1 
On 17/11/2020 19:43, Alex Hung wrote:
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/bios/mtrr/mtrr.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/src/bios/mtrr/mtrr.c b/src/bios/mtrr/mtrr.c
> index c9b77941..46edf92b 100644
> --- a/src/bios/mtrr/mtrr.c
> +++ b/src/bios/mtrr/mtrr.c
> @@ -53,6 +53,10 @@ static fwts_cpuinfo_x86 *fwts_cpuinfo;
>  #define AMD_SYS_CFG_MSR		0xC0010010
>  #define AMD_TOM2_MSR		0xC001001D
>  
> +#define MTRR_ENABLE		0x800
> +#define FIXED_MTRR_ENABLE	0x400
> +
> +
>  static	uint64_t mtrr_default;
>  static	uint64_t amd_tom2_addr;
>  static	bool amd_Tom2ForceMemTypeWB = false;
> @@ -594,6 +598,36 @@ static int mtrr_deinit(fwts_framework *fw)
>  	return FWTS_OK;
>  }
>  
> +static int mtrr_test0(fwts_framework *fw)
> +{
> +	uint64_t mtrr_def_msr;
> +
> +	if (fwts_cpu_readmsr(fw, 0, MTRR_DEF_TYPE_MSR, &mtrr_def_msr) != FWTS_OK) {
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRMSRDefaultNotAvailable",
> +			"MTRR_DEF_TYPE_MSR cannot be read from CPU.");
> +		return FWTS_ERROR;
> +	}
> +
> +	if (mtrr_def_msr & MTRR_ENABLE)
> +		fwts_passed(fw, "MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
> +	else
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRDisabled",
> +			"MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
> +			"all MTRRs are disabled ");
> +
> +	if (mtrr_def_msr & FIXED_MTRR_ENABLE)
> +		fwts_passed(fw, "fixed MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
> +	else
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRFixedRangeDisabled",
> +			"Fixed MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
> +			"all Fixed-range MTRRs are disabled ");
> +
> +	return FWTS_OK;
> +}
> +
>  static int mtrr_test1(fwts_framework *fw)
>  {
>  	return validate_iomem(fw);
> @@ -658,6 +692,7 @@ static int mtrr_test3(fwts_framework *fw)
>  }
>  
>  static fwts_framework_minor_test mtrr_tests[] = {
> +	{ mtrr_test0, "Validate MTRR default enabled." },
>  	{ mtrr_test1, "Validate the kernel MTRR IOMEM setup." },
>  	{ mtrr_test2, "Validate the MTRR setup across all processors." },
>  	{ mtrr_test3, "Test for AMD MtrrFixDramModEn being cleared by the BIOS." },
> 

Thanks Alex

Acked-by: Colin Ian King <colin.king@canonical.com>
Ivan Hu Nov. 20, 2020, 5:31 a.m. UTC | #2 
On 11/18/20 3:43 AM, Alex Hung wrote:
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/bios/mtrr/mtrr.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/src/bios/mtrr/mtrr.c b/src/bios/mtrr/mtrr.c
> index c9b77941..46edf92b 100644
> --- a/src/bios/mtrr/mtrr.c
> +++ b/src/bios/mtrr/mtrr.c
> @@ -53,6 +53,10 @@ static fwts_cpuinfo_x86 *fwts_cpuinfo;
>  #define AMD_SYS_CFG_MSR		0xC0010010
>  #define AMD_TOM2_MSR		0xC001001D
>  
> +#define MTRR_ENABLE		0x800
> +#define FIXED_MTRR_ENABLE	0x400
> +
> +
>  static	uint64_t mtrr_default;
>  static	uint64_t amd_tom2_addr;
>  static	bool amd_Tom2ForceMemTypeWB = false;
> @@ -594,6 +598,36 @@ static int mtrr_deinit(fwts_framework *fw)
>  	return FWTS_OK;
>  }
>  
> +static int mtrr_test0(fwts_framework *fw)
> +{
> +	uint64_t mtrr_def_msr;
> +
> +	if (fwts_cpu_readmsr(fw, 0, MTRR_DEF_TYPE_MSR, &mtrr_def_msr) != FWTS_OK) {
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRMSRDefaultNotAvailable",
> +			"MTRR_DEF_TYPE_MSR cannot be read from CPU.");
> +		return FWTS_ERROR;
> +	}
> +
> +	if (mtrr_def_msr & MTRR_ENABLE)
> +		fwts_passed(fw, "MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
> +	else
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRDisabled",
> +			"MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
> +			"all MTRRs are disabled ");
> +
> +	if (mtrr_def_msr & FIXED_MTRR_ENABLE)
> +		fwts_passed(fw, "fixed MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
> +	else
> +		fwts_failed(fw, LOG_LEVEL_CRITICAL,
> +			"MTRRFixedRangeDisabled",
> +			"Fixed MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
> +			"all Fixed-range MTRRs are disabled ");
> +
> +	return FWTS_OK;
> +}
> +
>  static int mtrr_test1(fwts_framework *fw)
>  {
>  	return validate_iomem(fw);
> @@ -658,6 +692,7 @@ static int mtrr_test3(fwts_framework *fw)
>  }
>  
>  static fwts_framework_minor_test mtrr_tests[] = {
> +	{ mtrr_test0, "Validate MTRR default enabled." },
>  	{ mtrr_test1, "Validate the kernel MTRR IOMEM setup." },
>  	{ mtrr_test2, "Validate the MTRR setup across all processors." },
>  	{ mtrr_test3, "Test for AMD MtrrFixDramModEn being cleared by the BIOS." },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
diff mbox series

Patch

diff --git a/src/bios/mtrr/mtrr.c b/src/bios/mtrr/mtrr.c
index c9b77941..46edf92b 100644
--- a/src/bios/mtrr/mtrr.c
+++ b/src/bios/mtrr/mtrr.c
@@ -53,6 +53,10 @@  static fwts_cpuinfo_x86 *fwts_cpuinfo;
 #define AMD_SYS_CFG_MSR		0xC0010010
 #define AMD_TOM2_MSR		0xC001001D
 
+#define MTRR_ENABLE		0x800
+#define FIXED_MTRR_ENABLE	0x400
+
+
 static	uint64_t mtrr_default;
 static	uint64_t amd_tom2_addr;
 static	bool amd_Tom2ForceMemTypeWB = false;
@@ -594,6 +598,36 @@  static int mtrr_deinit(fwts_framework *fw)
 	return FWTS_OK;
 }
 
+static int mtrr_test0(fwts_framework *fw)
+{
+	uint64_t mtrr_def_msr;
+
+	if (fwts_cpu_readmsr(fw, 0, MTRR_DEF_TYPE_MSR, &mtrr_def_msr) != FWTS_OK) {
+		fwts_failed(fw, LOG_LEVEL_CRITICAL,
+			"MTRRMSRDefaultNotAvailable",
+			"MTRR_DEF_TYPE_MSR cannot be read from CPU.");
+		return FWTS_ERROR;
+	}
+
+	if (mtrr_def_msr & MTRR_ENABLE)
+		fwts_passed(fw, "MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
+	else
+		fwts_failed(fw, LOG_LEVEL_CRITICAL,
+			"MTRRDisabled",
+			"MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
+			"all MTRRs are disabled ");
+
+	if (mtrr_def_msr & FIXED_MTRR_ENABLE)
+		fwts_passed(fw, "fixed MTRRs enabled flag is set in MTRR_DEF_TYPE MSR correctly.");
+	else
+		fwts_failed(fw, LOG_LEVEL_CRITICAL,
+			"MTRRFixedRangeDisabled",
+			"Fixed MTRRs enabled flag is clear in MTRR_DEF_TYPE MSR and "
+			"all Fixed-range MTRRs are disabled ");
+
+	return FWTS_OK;
+}
+
 static int mtrr_test1(fwts_framework *fw)
 {
 	return validate_iomem(fw);
@@ -658,6 +692,7 @@  static int mtrr_test3(fwts_framework *fw)
 }
 
 static fwts_framework_minor_test mtrr_tests[] = {
+	{ mtrr_test0, "Validate MTRR default enabled." },
 	{ mtrr_test1, "Validate the kernel MTRR IOMEM setup." },
 	{ mtrr_test2, "Validate the MTRR setup across all processors." },
 	{ mtrr_test3, "Test for AMD MtrrFixDramModEn being cleared by the BIOS." },