diff mbox series

cpu/msr: skip MSR MCG_CTL (0x17b) for AMD CPUS

Message ID 20201009043538.267977-1-alex.hung@canonical.com
State New
Headers show
Series cpu/msr: skip MSR MCG_CTL (0x17b) for AMD CPUS | expand

Commit Message

Alex Hung Oct. 9, 2020, 4:35 a.m. UTC
AMD CPU only report the extension MCA banks on CPU0.

BugLink: https://bugs.launchpad.net/fwts/+bug/1897220

Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

ivanhu Oct. 19, 2020, 3:40 a.m. UTC | #1
On 10/9/20 12:35 PM, Alex Hung wrote:
> AMD CPU only report the extension MCA banks on CPU0.
> 
> BugLink: https://bugs.launchpad.net/fwts/+bug/1897220
> 
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 3a8722c2..c4edc5b8 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -270,7 +270,9 @@ static const msr_info AMD_MSRs[] = {
>  	{ "MCG_CAP",			0x00000179,	0x0000000001ff0fffULL, NULL },
>  	  */
>  	{ "MCG_STATUS",			0x0000017a,	0xffffffffffffffffULL, NULL },
> +	/* MCG_CTL differs in Ryzen 4000 series and probably later series
>  	{ "MCG_CTL",			0x0000017b,	0xffffffffffffffffULL, NULL },
> +	*/
>  	{ "MTRR_PHYSBASE0",		0x00000200,	0xffffffffffffffffULL, NULL },
>  	{ "MTRR_PHYSMASK0",		0x00000201,	0xffffffffffffffffULL, NULL },
>  	{ "MTRR_PHYSBASE1",		0x00000202,	0xffffffffffffffffULL, NULL },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>
diff mbox series

Patch

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 3a8722c2..c4edc5b8 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -270,7 +270,9 @@  static const msr_info AMD_MSRs[] = {
 	{ "MCG_CAP",			0x00000179,	0x0000000001ff0fffULL, NULL },
 	  */
 	{ "MCG_STATUS",			0x0000017a,	0xffffffffffffffffULL, NULL },
+	/* MCG_CTL differs in Ryzen 4000 series and probably later series
 	{ "MCG_CTL",			0x0000017b,	0xffffffffffffffffULL, NULL },
+	*/
 	{ "MTRR_PHYSBASE0",		0x00000200,	0xffffffffffffffffULL, NULL },
 	{ "MTRR_PHYSMASK0",		0x00000201,	0xffffffffffffffffULL, NULL },
 	{ "MTRR_PHYSBASE1",		0x00000202,	0xffffffffffffffffULL, NULL },