From patchwork Fri Jul 15 14:54:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Hung X-Patchwork-Id: 648860 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) by ozlabs.org (Postfix) with ESMTP id 3rrbG16pzCz9s5Q; Sat, 16 Jul 2016 00:55:05 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1bO4W4-0003lm-CD; Fri, 15 Jul 2016 14:55:00 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1bO4Vz-0003lf-AA for fwts-devel@lists.ubuntu.com; Fri, 15 Jul 2016 14:54:55 +0000 Received: from [175.182.109.84] (helo=canonical.com) by youngberry.canonical.com with esmtpsa (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.76) (envelope-from ) id 1bO4Vy-0005Jz-Dd; Fri, 15 Jul 2016 14:54:55 +0000 From: Alex Hung To: fwts-devel@lists.ubuntu.com Subject: [PATCH][V2] bios: mtrr: check MTRR default memory type Date: Fri, 15 Jul 2016 22:54:47 +0800 Message-Id: <1468594487-15591-1-git-send-email-alex.hung@canonical.com> X-Mailer: git-send-email 2.7.4 X-BeenThere: fwts-devel@lists.ubuntu.com X-Mailman-Version: 2.1.14 Precedence: list List-Id: Firmware Test Suite Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: fwts-devel-bounces@lists.ubuntu.com Sender: fwts-devel-bounces@lists.ubuntu.com IA32_MTRR_DEF_TYPE MSR sets the default properties of the regions of physical memory that are not encompassed by MTRRs. Especially, Bit 0 to 7 indicates the default memory type. Signed-off-by: Alex Hung --- src/bios/mtrr/mtrr.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/bios/mtrr/mtrr.c b/src/bios/mtrr/mtrr.c index 18e1a29..07d9bbe 100644 --- a/src/bios/mtrr/mtrr.c +++ b/src/bios/mtrr/mtrr.c @@ -49,6 +49,8 @@ static fwts_cpuinfo_x86 *fwts_cpuinfo; #define DISABLED 0x0040 #define UNKNOWN 0x0080 +#define MTRR_DEF_TYPE_MSR 0x2FF + struct mtrr_entry { uint8_t reg; uint64_t start; @@ -170,6 +172,7 @@ static int cache_types(uint64_t start, uint64_t end) fwts_list_link *item; struct mtrr_entry *entry; int type = 0; + uint64_t mtrr_default = UNCACHED; fwts_list_foreach(item, mtrr_list) { entry = fwts_list_data(struct mtrr_entry*, item); @@ -198,6 +201,35 @@ restart: /* if there is no full coverage it's also uncached */ if (start != end) type |= DEFAULT; + + if (!fwts_cpu_readmsr(0, MTRR_DEF_TYPE_MSR, &mtrr_default)) { + switch (mtrr_default & 0xFF) { + case 0: + mtrr_default = UNCACHED; + break; + case 1: + mtrr_default = WRITE_COMBINING; + break; + case 4: + mtrr_default = WRITE_THROUGH; + break; + case 5: + mtrr_default = WRITE_PROTECT; + break; + case 6: + mtrr_default = WRITE_BACK; + break; + default: + mtrr_default = UNKNOWN; + break; + } + + if ((type & DEFAULT) && mtrr_default != UNCACHED) { + type &= ~DEFAULT; + type |= mtrr_default; + } + } + return type; }