| Message ID | tencent_947689E304AE5A4C7A48682311DF8920B106@qq.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | riscv: add initial support for SpacemiT K1 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Jun 17, 2024 at 01:20:47AM +0800, Yangyu Chen wrote: > The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1 > SoC. > > Link: https://www.spacemit.com/en/spacemit-x60-core/ > nit: Delete the blank line > Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d87dd50f1a4b..5ad9cb410335 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -46,6 +46,7 @@ properties: > - sifive,u7 > - sifive,u74 > - sifive,u74-mc > + - spacemit,x60 > - thead,c906 > - thead,c910 > - thead,c920 > -- > 2.45.1 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..5ad9cb410335 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -46,6 +46,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x60 - thead,c906 - thead,c910 - thead,c920
The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1 SoC. Link: https://www.spacemit.com/en/spacemit-x60-core/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)