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Wed, 25 Oct 2023 11:56:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGRHDA8d43i/0eqTtRETVi4ef1AAWHZvlYua8G+9qwUeJ5hvjbzmci7qiMP/aXUn13Et1Ecrw6N0+hOCNM2Ze0= Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Received: by 2002:a05:622a:14e:b0:41e:172f:6e78 with SMTP id v14-20020a05622a014e00b0041e172f6e78mr15135502qtw.29.1698260201944; Wed, 25 Oct 2023 11:56:41 -0700 (PDT) Received: from 348282803490 named unknown by gmailapi.google.com with HTTPREST; Wed, 25 Oct 2023 11:56:41 -0700 From: Emil Renner Berthing Date: Wed, 25 Oct 2023 11:56:41 -0700 Message-ID: Subject: [PATCH 3/4] dt-bindings: cache: sifive,ccache0: Add sifive,cache-ops property To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Emil Renner Berthing This cache controller also supports flushing cache lines by writing their address to a register. This can be used for cache management on SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension such as the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing --- Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ 1 file changed, 5 insertions(+) - $ref: /schemas/cache-controller.yaml# diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..36ae6f48ce0b 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -81,6 +81,11 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. + sifive,cache-ops: + type: boolean + description: | + Use this cache controller for non-standard cache management operations. + allOf: