From patchwork Tue Mar 10 14:16:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Punnaiah Choudary Kalluri X-Patchwork-Id: 448538 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6FEDB14016A for ; Wed, 11 Mar 2015 01:49:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752278AbbCJOtr (ORCPT ); Tue, 10 Mar 2015 10:49:47 -0400 Received: from mail-bn1on0090.outbound.protection.outlook.com ([157.56.110.90]:21907 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752019AbbCJOtq (ORCPT ); Tue, 10 Mar 2015 10:49:46 -0400 X-Greylist: delayed 1983 seconds by postgrey-1.27 at vger.kernel.org; Tue, 10 Mar 2015 10:49:45 EDT Received: from BN1AFFO11FD032.protection.gbl (10.58.52.31) by BN1AFFO11HUB057.protection.gbl (10.58.52.208) with Microsoft SMTP Server (TLS) id 15.1.112.13; Tue, 10 Mar 2015 14:16:40 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BN1AFFO11FD032.mail.protection.outlook.com (10.58.52.186) with Microsoft SMTP Server (TLS) id 15.1.112.13 via Frontend Transport; Tue, 10 Mar 2015 14:16:39 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1YVKtZ-0004Ac-Ni; Tue, 10 Mar 2015 07:12:29 -0700 From: Punnaiah Choudary Kalluri To: , , , , CC: , , , , , Punnaiah Choudary Kalluri Subject: [PATCH] dma: Add Xilinx ZDMA device tree Binding Documentation Date: Tue, 10 Mar 2015 19:46:23 +0530 X-Mailer: git-send-email 1.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-7.5.0.1018-21388.005 X-TM-AS-User-Approved-Sender: Yes;Yes;Yes Message-ID: X-EOPAttributedMessage: 0 Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=punnaiah.choudary.kalluri@xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10009020)(6009001)(438002)(189002)(199003)(229853001)(87936001)(50986999)(104016003)(19580395003)(19580405001)(6806004)(46102003)(106466001)(50226001)(33656002)(53416004)(50466002)(92566002)(86362001)(62966003)(77156002)(47776003)(48376002)(74316001)(551934003)(107986001)(23106004); DIR:OUT; SFP:1101; SCL:1; SRVR:BN1AFFO11HUB057; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1AFFO11HUB057; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002009)(5005006); SRVR:BN1AFFO11HUB057; BCL:0; PCL:0; RULEID:; SRVR:BN1AFFO11HUB057; X-Forefront-PRVS: 051158ECBB X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2015 14:16:39.9141 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1AFFO11HUB057 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Device-tree binding documentation for Xilinx ZDMA Engine Signed-off-by: Punnaiah Choudary Kalluri --- .../devicetree/bindings/dma/xilinx/zdma.txt | 76 ++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt new file mode 100644 index 0000000..399a3bc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt @@ -0,0 +1,76 @@ +Xilinx ZDMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Xilinx ZynqMP has two instances of general purpose DMA(ZDMA). +one is located in FPD(full power domain) and other is located in +LPD(low power domain). + +ZDMA instance located in FPD is referred as FPDMA and instance located +in LPD is referred as LPDMA. + +FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte. +LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte. + +Each channel in a instance has its own address space and interrupt line +but shares common reference and APB clock. So, each channel will be treated +as a standalone dma device. +Since its a general purpose dma controller, it has a rich set of configurable +options with respect to data and descriptor attributes. + +Required properties: +- compatible: Should be "xlnx,fpdma-1.0" or "xlnx,lpdma-1.0" +- reg: Memory map for dma module access. +- interrupt-parent: Interrupt controller the interrupt is routed through +- interrupts: Should contain DMA channel interrupt. +- xlnx,id: Channel Id + +Optional properties: +- xlnx,include-sg: Indicates the controller to operate in simple or scatter + gather dma mode +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for + source AXI transaction +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data +- xlnx,src-issue: Number of AXI outstanding transactions on source side +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the + descriptor read are marked Non-coherent +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the + source descriptor payload are marked Non-coherent +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the + dst descriptor payload are marked Non-coherent +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch +- xlnx,src-axi-qos: AXI QOS bits to be used for data read +- xlnx,dst-axi-qos: Axi QOS bits to be used for data write +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch +- xlnx,desc-axi-cache: AXI cache bits to be used for data read +- xlnx,desc-axi-cache: AXI cache bits to be used for data write +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values + i.e 1,2,4,8 and 16. +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values + i.e 1,2,4,8 and 16. + +Example: +++++++++ +fpdma0: dma@fd500000 { + compatible = "xlnx,fpdma-1.0"; + reg = <0x0 0xfd500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + xlnx,include-sg; + xlnx,overfetch; + xlnx,ratectrl = <0>; + xlnx,src-issue = <16>; + xlnx,id = <0>; + xlnx,desc-axi-cohrnt; + xlnx,src-axi-cohrnt; + xlnx,dst-axi-cohrnt; + xlnx,desc-axi-qos = <0>; + xlnx,desc-axi-cache = <0>; + xlnx,src-axi-qos = <0>; + xlnx,src-axi-cache = <2>; + xlnx,dst-axi-qos = <0>; + xlnx,dst-axi-cache = <2>; + xlnx,src-burst-len = <4>; + xlnx,dst-burst-len = <4>; +}; +