diff mbox

dma: Add Xilinx ZDMA device tree Binding Documentation

Message ID BN1AFFO11FD032F933FA09686353911532C8180@BN1AFFO11FD032.protection.gbl
State New, archived
Headers show

Commit Message

Punnaiah Choudary Kalluri March 10, 2015, 2:16 p.m. UTC
Device-tree binding documentation for Xilinx ZDMA Engine

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
 .../devicetree/bindings/dma/xilinx/zdma.txt        |   76 ++++++++++++++++++++
 1 files changed, 76 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt

Comments

Josh Cartwright March 10, 2015, 11:57 p.m. UTC | #1
On Tue, Mar 10, 2015 at 07:46:23PM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx ZDMA Engine
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---

Hey Punnaiah-

Was this intended to be sent out with a driver?

>  .../devicetree/bindings/dma/xilinx/zdma.txt        |   76 ++++++++++++++++++++
>  1 files changed, 76 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> new file mode 100644
> index 0000000..399a3bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> @@ -0,0 +1,76 @@
> +Xilinx ZDMA engine, it does support memory to memory transfers,
> +memory to device and device to memory transfers. It also has flow
> +control and rate control support for slave/peripheral dma access.
> +
> +Xilinx ZynqMP has two instances of general purpose DMA(ZDMA).
> +one is located in FPD(full power domain) and other is located in
> +LPD(low power domain).
> +
> +ZDMA instance located in FPD is referred as FPDMA and instance located
> +in LPD is referred as LPDMA.
> +
> +FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte.
> +LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte.
> +
> +Each channel in a instance has its own address space and interrupt line
                   ^an

> +but shares common reference and APB clock. So, each channel will be treated
> +as a standalone dma device.

Does your example below then describe only a single channel?  Or, should
I expect to see sub-nodes representing each of the dma channels?

> +Since its a general purpose dma controller, it has a rich set of configurable
> +options with respect to data and descriptor attributes.
> +
> +Required properties:
> +- compatible: Should be "xlnx,fpdma-1.0" or "xlnx,lpdma-1.0"
> +- reg: Memory map for dma module access.
> +- interrupt-parent: Interrupt controller the interrupt is routed through
> +- interrupts: Should contain DMA channel interrupt.
> +- xlnx,id: Channel Id

I would have expected, as a dma controller, to see a #dma-cells here,
and a tie-in to the existing Documentation/devicetree/bindings/dma/dma.txt documentation.

  Josh
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Soren Brinkmann March 11, 2015, 12:01 a.m. UTC | #2
On Tue, 2015-03-10 at 07:46PM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx ZDMA Engine
> 
> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
> ---
>  .../devicetree/bindings/dma/xilinx/zdma.txt        |   76 ++++++++++++++++++++
>  1 files changed, 76 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> new file mode 100644
> index 0000000..399a3bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
> @@ -0,0 +1,76 @@
> +Xilinx ZDMA engine, it does support memory to memory transfers,
> +memory to device and device to memory transfers. It also has flow
> +control and rate control support for slave/peripheral dma access.
> +
> +Xilinx ZynqMP has two instances of general purpose DMA(ZDMA).
> +one is located in FPD(full power domain) and other is located in
> +LPD(low power domain).
> +
> +ZDMA instance located in FPD is referred as FPDMA and instance located
> +in LPD is referred as LPDMA.
> +
> +FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte.
> +LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte.

All these implementation details are good background information, but
shouldn't be part of the binding.

	Sören
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punnaiah choudary kalluri March 11, 2015, 2:48 a.m. UTC | #3
On Wed, Mar 11, 2015 at 5:27 AM, Josh Cartwright <joshc@ni.com> wrote:
> On Tue, Mar 10, 2015 at 07:46:23PM +0530, Punnaiah Choudary Kalluri wrote:
>> Device-tree binding documentation for Xilinx ZDMA Engine
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> ---
>
> Hey Punnaiah-
>
> Was this intended to be sent out with a driver?

First I would like to complete my review for device tree bindings and
then planning to send the driver for review. please let me know if this is not
the right way to do?

>
>>  .../devicetree/bindings/dma/xilinx/zdma.txt        |   76 ++++++++++++++++++++
>>  1 files changed, 76 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>> new file mode 100644
>> index 0000000..399a3bc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>> @@ -0,0 +1,76 @@
>> +Xilinx ZDMA engine, it does support memory to memory transfers,
>> +memory to device and device to memory transfers. It also has flow
>> +control and rate control support for slave/peripheral dma access.
>> +
>> +Xilinx ZynqMP has two instances of general purpose DMA(ZDMA).
>> +one is located in FPD(full power domain) and other is located in
>> +LPD(low power domain).
>> +
>> +ZDMA instance located in FPD is referred as FPDMA and instance located
>> +in LPD is referred as LPDMA.
>> +
>> +FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte.
>> +LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte.
>> +
>> +Each channel in a instance has its own address space and interrupt line
>                    ^an
>
>> +but shares common reference and APB clock. So, each channel will be treated
>> +as a standalone dma device.
>
> Does your example below then describe only a single channel?  Or, should
> I expect to see sub-nodes representing each of the dma channels?

As said above each channel has its own register space and separate interrupt,
i am treating each dma channel as standalone dma controller i.e dma
controller with
single channel. So, the below node describes for single channel and
other channel
nodes can follow the below example.

>
>> +Since its a general purpose dma controller, it has a rich set of configurable
>> +options with respect to data and descriptor attributes.
>> +
>> +Required properties:
>> +- compatible: Should be "xlnx,fpdma-1.0" or "xlnx,lpdma-1.0"
>> +- reg: Memory map for dma module access.
>> +- interrupt-parent: Interrupt controller the interrupt is routed through
>> +- interrupts: Should contain DMA channel interrupt.
>> +- xlnx,id: Channel Id
>
> I would have expected, as a dma controller, to see a #dma-cells here,
> and a tie-in to the existing Documentation/devicetree/bindings/dma/dma.txt documentation.

Ok i will take care of this in next version. thanks.

Regards,
Punnaiah
>
>   Josh
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punnaiah choudary kalluri March 11, 2015, 2:51 a.m. UTC | #4
On Wed, Mar 11, 2015 at 5:31 AM, Sören Brinkmann
<soren.brinkmann@xilinx.com> wrote:
> On Tue, 2015-03-10 at 07:46PM +0530, Punnaiah Choudary Kalluri wrote:
>> Device-tree binding documentation for Xilinx ZDMA Engine
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
>> ---
>>  .../devicetree/bindings/dma/xilinx/zdma.txt        |   76 ++++++++++++++++++++
>>  1 files changed, 76 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>> new file mode 100644
>> index 0000000..399a3bc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
>> @@ -0,0 +1,76 @@
>> +Xilinx ZDMA engine, it does support memory to memory transfers,
>> +memory to device and device to memory transfers. It also has flow
>> +control and rate control support for slave/peripheral dma access.
>> +
>> +Xilinx ZynqMP has two instances of general purpose DMA(ZDMA).
>> +one is located in FPD(full power domain) and other is located in
>> +LPD(low power domain).
>> +
>> +ZDMA instance located in FPD is referred as FPDMA and instance located
>> +in LPD is referred as LPDMA.
>> +
>> +FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte.
>> +LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte.
>
> All these implementation details are good background information, but
> shouldn't be part of the binding.

Ok. i will remove then.

Thanks.
Punnaiah
>
>         Sören
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/dma/xilinx/zdma.txt b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
new file mode 100644
index 0000000..399a3bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/zdma.txt
@@ -0,0 +1,76 @@ 
+Xilinx ZDMA engine, it does support memory to memory transfers,
+memory to device and device to memory transfers. It also has flow
+control and rate control support for slave/peripheral dma access.
+
+Xilinx ZynqMP has two instances of general purpose DMA(ZDMA).
+one is located in FPD(full power domain) and other is located in
+LPD(low power domain).
+
+ZDMA instance located in FPD is referred as FPDMA and instance located
+in LPD is referred as LPDMA.
+
+FPDMA is configured with 8 DMA channels and AXI bus width is 128 byte.
+LPDMA is configured with 8 DMA channels and AXI bus width is 64 byte.
+
+Each channel in a instance has its own address space and interrupt line
+but shares common reference and APB clock. So, each channel will be treated
+as a standalone dma device.
+Since its a general purpose dma controller, it has a rich set of configurable
+options with respect to data and descriptor attributes.
+
+Required properties:
+- compatible: Should be "xlnx,fpdma-1.0" or "xlnx,lpdma-1.0"
+- reg: Memory map for dma module access.
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Should contain DMA channel interrupt.
+- xlnx,id: Channel Id
+
+Optional properties:
+- xlnx,include-sg: Indicates the controller to operate in simple or scatter
+		   gather dma mode
+- xlnx,ratectrl: Scheduling interval in terms of clock cycles for
+		 source AXI transaction
+- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data
+- xlnx,src-issue: Number of AXI outstanding transactions on source side
+- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the
+			descriptor read are marked Non-coherent
+- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the
+			source descriptor payload are marked Non-coherent
+- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the
+			dst descriptor payload are marked Non-coherent
+- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch
+- xlnx,src-axi-qos: AXI QOS bits to be used for data read
+- xlnx,dst-axi-qos: Axi QOS bits to be used for data write
+- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch
+- xlnx,desc-axi-cache: AXI cache bits to be used for data read
+- xlnx,desc-axi-cache: AXI cache bits to be used for data write
+- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values
+		      i.e 1,2,4,8 and 16.
+- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values
+		      i.e 1,2,4,8 and 16.
+
+Example:
+++++++++
+fpdma0: dma@fd500000 {
+	compatible = "xlnx,fpdma-1.0";
+	reg = <0x0 0xfd500000 0x1000>;
+	interrupt-parent = <&gic>;
+	interrupts = <0 117 4>;
+	xlnx,include-sg;
+	xlnx,overfetch;
+	xlnx,ratectrl = <0>;
+	xlnx,src-issue = <16>;
+	xlnx,id = <0>;
+	xlnx,desc-axi-cohrnt;
+	xlnx,src-axi-cohrnt;
+	xlnx,dst-axi-cohrnt;
+	xlnx,desc-axi-qos = <0>;
+	xlnx,desc-axi-cache = <0>;
+	xlnx,src-axi-qos = <0>;
+	xlnx,src-axi-cache = <2>;
+	xlnx,dst-axi-qos = <0>;
+	xlnx,dst-axi-cache = <2>;
+	xlnx,src-burst-len = <4>;
+	xlnx,dst-burst-len = <4>;
+};
+