From patchwork Sun Feb 2 18:31:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davor Joja X-Patchwork-Id: 316029 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 003262C009A for ; Mon, 3 Feb 2014 05:31:38 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751999AbaBBSbi (ORCPT ); Sun, 2 Feb 2014 13:31:38 -0500 Received: from mail.logicbricks.com ([89.201.165.134]:20518 "EHLO mail.logicbricks.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751913AbaBBSbh (ORCPT ); Sun, 2 Feb 2014 13:31:37 -0500 From: Davor Joja To: CC: , Davor Joja Subject: [RFC 2/2] Documentation: devicetree: bindings: drm: Xylon binding Date: Sun, 2 Feb 2014 19:31:23 +0100 X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1391365883-18071-1-git-send-email-davorjoja@logicbricks.com> References: <1391365883-18071-1-git-send-email-davorjoja@logicbricks.com> MIME-Version: 1.0 X-Originating-IP: [192.168.0.76] Message-ID: <6344696d-861e-4cfb-bc40-bb49c092c42b@mail.xylon.local> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Xylon binding of DRM driver and logiCVC IP core. Signed-off-by: Davor Joja --- .../devicetree/bindings/drm/xylon/logicvc.txt | 79 ++++++++++++++++++++ .../devicetree/bindings/drm/xylon/xylon_drm.txt | 24 ++++++ 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/xylon/logicvc.txt create mode 100644 Documentation/devicetree/bindings/drm/xylon/xylon_drm.txt diff --git a/Documentation/devicetree/bindings/drm/xylon/logicvc.txt b/Documentation/devicetree/bindings/drm/xylon/logicvc.txt new file mode 100644 index 0000000..505e655 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xylon/logicvc.txt @@ -0,0 +1,79 @@ +Binding for Xylon configurable video controller logiCVC IP core + +Required properties: + - compatible: value must be "xylon,logicvc-4.00.a" + - reg: MMIO base address and size of the logiCVC IP core address space + - interrupts-parent: the phandle for interrupt controller + - interrupts: the interrupt number + - background-layer-bits-per-pixel: background layer bits per pixel (16, 32) + if omitted, last available layer is logiCVC standard layer, which has its + own video memory of specific size, color format and specified + bits per pixel + if 16 or 32, last available layer is logiCVC background layer, + with only specified bits per pixel value + - interface: logiCVC to display physical interface + (0=Parallel, 1=ITU656) + - color-space: logiCVC to display physical color space + (0=RGB, 1=YCbCr 4:2:2, 2=YCbCr 4:4:4) + - is-readable-regs: all logiCVC registers are available for reading + if omitted, only Interrupt Status, Power Control and IP Version registers + are available for reading + - is-size-position: logiCVC functionality for controlling on screen layer size + and position is available + if omitted, functionality is not available + - pixel-stride: layer video memory width in pixels + common for all available logiCVC standard layers + - layer_0: layer has its own configuration described with below properties + - bits-per-pixel: layer bits per pixel configuration (16, 32) + layer is configured to be used with specific pixel width in bits + pixels written to layer video memory must match in size to configured + bits per pixel value + - format: layer format (0=RGB, 1=YCbCr) + layer is configured to be used with specific color format + pixels written to layer video memory must match specified color format + - transparency: layer transparency (0=Layer, 1=Pixel) + logiCVC layer can be configured to have transparency control on + layer or pixel level + "Layer" mode enables controlling of layer transparency by changing + alpha value in single logiCVC register + "Pixel" mode enables controlling of pixel transparency by changing + dedicated alpha bits of specific pixel in video memory + +Example: + + logicvc_0: logicvc@40000000 { + compatible = "xylon,logicvc-4.00.a"; + reg = <0x40000000 0x6000>; + interrupt-parent = <&gic_0>; + interrupts = <0 59 4>; + background-layer-bits-per-pixel = <32>; + interface = <0>; + color-space = <1>; + is-readable-regs; + is-size-position; + pixel-stride = <2048>; + layer_0 { + address = <0x30000000>; + bits-per-pixel = <16>; + format = <0>; + transparency = <0>; + }; + layer_1 { + address = <0x30500000>; + bits-per-pixel = <32>; + format = <0>; + transparency = <0>; + }; + layer_2 { + address = <0x30E00000>; + bits-per-pixel = <32>; + format = <0>; + transparency = <1>; + }; + layer_3 { + address = <0x31700000>; + bits-per-pixel = <16>; + format = <1>; + transparency = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/drm/xylon/xylon_drm.txt b/Documentation/devicetree/bindings/drm/xylon/xylon_drm.txt new file mode 100644 index 0000000..da4940e --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xylon/xylon_drm.txt @@ -0,0 +1,24 @@ +Binding for Xylon DRM driver + +Xylon DRM driver supports the Xylon configurable video controller +logiCVC FPGA IP core device. + +On ZC702, ZC706, ZED boards, logiCVC uses SI570 CCF driver for pixel clock +generation, and ADV7511 DRM encoder driver to set video encoding configuration. + +Required properties: + - compatible: value should be "xylon,drm-1.00.a". + - clocks: the phandle for the pixel clock generator + - device: the phandle for logiCVC video controller device + - encoder: the phandle for the video encoder + - private-plane: logiCVC layer id used for DRM driver private plane + +Example: + + xylon_drm { + compatible = "xylon,drm-1.00.a"; + clocks = <&si570>; + device = <&logicvc_0>; + encoder = <&adv7511>; + private-plane = <0>; + };