From patchwork Wed Jul 20 03:41:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: apronin@chromium.org X-Patchwork-Id: 650538 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rvN5M3mZmz9stY for ; Wed, 20 Jul 2016 13:42:15 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b=iuHEr5yz; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753255AbcGTDlj (ORCPT ); Tue, 19 Jul 2016 23:41:39 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:33036 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753100AbcGTDl3 (ORCPT ); Tue, 19 Jul 2016 23:41:29 -0400 Received: by mail-pf0-f182.google.com with SMTP id y134so14166329pfg.0 for ; Tue, 19 Jul 2016 20:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=sLcd/rys0MCiMBkCCgMsnH2n3WHi8GTe8xLGrVTiVgU=; b=iuHEr5yzHwmlfMf5SGzKTaVnUiJvWONnMWsOxtZmVa3j2kUYp0K3wYK5OtEb1dEpr0 Fpxs9nNEfv6QkPL4UAETcOR5zBYZR19pZB0A5F/aRAgPUxVQ0tdrrBDCjDxXc8/NbIMd KwdOyAX19aHBnPIDb+YRhXo2PTuoOt4+f8qys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=sLcd/rys0MCiMBkCCgMsnH2n3WHi8GTe8xLGrVTiVgU=; b=jguqLQqplA/ADDC8jWCNA+mjgrDswT7fQqg+7MJ9XGwWWzHecuwODGno8d7F/4blpl Rnw5bfjVBPPZW/ovDk1inplwIaxUzsiNA//Y2mWbnyHXqs6ewTQP2HanZrB5ZtSdWURi Wq0ToBfZn6oZyJeNL5r7VbCeVeJEIqtErBIbh8AVt0SOXOssOr4bcLQv1aDXTBkhybBZ uvb9hGBRDMMDTvPncX+aockiQa0y7RgmLF+LXeKzJ0+I16Cl+kvp27Cpzm5gkHk/BGwO /xw0LJtu7kn2Ej9d3BU8D6YvNynxJCTb5bdmhToUnrYlyllqDV7BhMZeT261wVEnLMy1 m3Vw== X-Gm-Message-State: ALyK8tKILMTFb1EjNl0VPvrDorL0aHqKn3+xRe3NbiZZRtrssyvaJKS0gKighhT8hb8OMBbL X-Received: by 10.98.10.148 with SMTP id 20mr60934141pfk.154.1468986089187; Tue, 19 Jul 2016 20:41:29 -0700 (PDT) Received: from apronin0.mtv.corp.google.com ([172.22.64.136]) by smtp.gmail.com with ESMTPSA id 132sm584930pfu.6.2016.07.19.20.41.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Jul 2016 20:41:28 -0700 (PDT) From: Andrey Pronin To: Jarkko Sakkinen Cc: Peter Huewe , Marcel Selhorst , Jason Gunthorpe , tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, Christophe Ricard , Andrey Pronin , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: [PATCH v2 1/2] tpm: devicetree: document properties for cr50 Date: Tue, 19 Jul 2016 20:41:24 -0700 Message-Id: <5274cc806888a709c639e701dad894543885b2c9.1468985673.git.apronin@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: References: <1468549218-19215-1-git-send-email-apronin@chromium.org> In-Reply-To: References: <1468549218-19215-1-git-send-email-apronin@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Several timing-related properties that may differ from one firmware version to another are added to devicetree. Document these properties. Signed-off-by: Andrey Pronin --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..f212b6b --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,32 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Optional properties: +- access-delay-ms: Required delay between subsequent transactions on SPI. +- sleep-delay-ms: Time after the last SPI activity, after which the chip + may go to sleep. +- wake-start-delay-ms: Time after initiating wake up before the chip is + ready to accept commands over SPI. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + + access-delay-ms = <2>; + sleep-delay-ms = <1000>; + wake-start-delay-ms = <60>; + }; +};