From patchwork Wed Jan 31 20:27:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 868067 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=cogentembedded-com.20150623.gappssmtp.com header.i=@cogentembedded-com.20150623.gappssmtp.com header.b="PKzPql49"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zWvvF1JQsz9ryr for ; Thu, 1 Feb 2018 07:27:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751797AbeAaU1v (ORCPT ); Wed, 31 Jan 2018 15:27:51 -0500 Received: from mail-lf0-f65.google.com ([209.85.215.65]:45395 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751579AbeAaU1u (ORCPT ); Wed, 31 Jan 2018 15:27:50 -0500 Received: by mail-lf0-f65.google.com with SMTP id x196so22693303lfd.12 for ; Wed, 31 Jan 2018 12:27:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3/UcJccws0mZfI1q2ahECE4Sty4TTl0f1bYT1ADsjXc=; b=PKzPql49sOd8wIW0YOS8cyuLQcvjZvVUyAY1szMZBQ5MG/B6X8dvSuxPPB5toW6NTJ mD/c9LKv2eXGyOgHmqFLJJeHkqcO+F6239x21NKdXuX8inUhuxYTpt9TuD0HawVHJQL8 fn3A+7V7yKuRrYDUQkJqxKr7v+u+MlbEcT+9iNbukiHutqz53u7S4xmdHHUALv7iIRdu 8Un/Q8VbJGa3aW9SPm4F+nF9PVJuk/hMnmBC720dow8kHlsiLnP06RASEqLwOptIjvhQ zRONqf4gE5eugB6PJNxJRLdXmkXRT4w1+FZLjBZGJxiPv4LW4aytkh7j0XNCzatOngkQ uL+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=3/UcJccws0mZfI1q2ahECE4Sty4TTl0f1bYT1ADsjXc=; b=Zpufsuiwcp82WOQ7QvMTxUix5zIgSw495+xUJ9Ky1nn63mTZlfrlLG1b91o27PxCxM R9uKOhsTcvlK8y5st9jX1QYQsgS/Ozu6XUwI8PyEEI4Vzz6lSFKJH+j1+h/KtSJWCr5l xJ44/MTEtMdnU7n3XZwUh49zVXIdorPp1syl8KVEsQNGqqyDlwHdapLTeL3Q9IDjii5v yhkhgruZfQEhwaX9iy4RQGtLFEeNmMupqnaQmk4VOMdJM/QA2eWP0ez3k4bWQ9GqMOz5 Qtw+clvfTFPvVujhI047o5RbfBBj0xo78qN1R5uALtVGw98GTW9KVM/GcKC9di6M+8FR dJ4A== X-Gm-Message-State: AKwxytevcxvAdZezcquuWhZGXIdFuOQp43rHLXGuvY8gJS2cYlO4hBzO aU3e9unkun/Geh+aAO99T/cSLA== X-Google-Smtp-Source: AH8x226NZwg7iuFVH/PwbTpkPNNEtPjAc8VBiBaJcz2UFVwxL44MXj62RRo5PdRUVAemnppkduCx2w== X-Received: by 10.25.154.205 with SMTP id c196mr19622868lfe.52.1517430469510; Wed, 31 Jan 2018 12:27:49 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.86.195]) by smtp.gmail.com with ESMTPSA id d132sm3976150lfd.69.2018.01.31.12.27.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jan 2018 12:27:48 -0800 (PST) Subject: [PATCH 1/2] dt-bindings: clock: add R8A77980 CPG core clock definitions From: Sergei Shtylyov To: Rob Herring , "devicetree@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" Cc: Mark Rutland References: <5b7895ac-11c1-ac2d-837b-56726bc6226a@cogentembedded.com> Organization: Cogent Embedded Message-ID: <4281b305-ff0d-cf56-ce6b-dff4589c39f6@cogentembedded.com> Date: Wed, 31 Jan 2018 23:27:47 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <5b7895ac-11c1-ac2d-837b-56726bc6226a@cogentembedded.com> Content-Language: en-MW Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add macros usable by the device tree sources to reference the R8A77980 CPG core clocks by index. The data come from the table 8.2e of the R-Car Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct, 2017), however I had to add the Z2 clock which is somehow present only on the figure 8.1e... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- include/dt-bindings/clock/r8a77980-cpg-mssr.h | 51 ++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h =================================================================== --- /dev/null +++ renesas-drivers/include/dt-bindings/clock/r8a77980-cpg-mssr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ + +#include + +/* r8a77980 CPG Core Clocks */ +#define R8A77980_CLK_Z2 0 +#define R8A77980_CLK_ZR 1 +#define R8A77980_CLK_ZTR 2 +#define R8A77980_CLK_ZTRD2 3 +#define R8A77980_CLK_ZT 4 +#define R8A77980_CLK_ZX 5 +#define R8A77980_CLK_S0D1 6 +#define R8A77980_CLK_S0D2 7 +#define R8A77980_CLK_S0D3 8 +#define R8A77980_CLK_S0D4 9 +#define R8A77980_CLK_S0D6 10 +#define R8A77980_CLK_S0D12 11 +#define R8A77980_CLK_S0D24 12 +#define R8A77980_CLK_S1D1 13 +#define R8A77980_CLK_S1D2 14 +#define R8A77980_CLK_S1D4 15 +#define R8A77980_CLK_S2D1 16 +#define R8A77980_CLK_S2D2 17 +#define R8A77980_CLK_S2D4 18 +#define R8A77980_CLK_S3D1 19 +#define R8A77980_CLK_S3D2 20 +#define R8A77980_CLK_S3D4 21 +#define R8A77980_CLK_LB 22 +#define R8A77980_CLK_CL 23 +#define R8A77980_CLK_ZB3 24 +#define R8A77980_CLK_ZB3D2 25 +#define R8A77980_CLK_ZB3D4 26 +#define R8A77980_CLK_SD0H 27 +#define R8A77980_CLK_SD0 28 +#define R8A77980_CLK_RPC 29 +#define R8A77980_CLK_RPCD2 30 +#define R8A77980_CLK_MSO 31 +#define R8A77980_CLK_CANFD 32 +#define R8A77980_CLK_CSI0 33 +#define R8A77980_CLK_CP 34 +#define R8A77980_CLK_CPEX 35 +#define R8A77980_CLK_R 36 +#define R8A77980_CLK_OSC 37 + +#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */