From patchwork Tue Jan 6 22:39:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 425862 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5CBCE1400EA for ; Wed, 7 Jan 2015 09:39:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751574AbbAFWj5 (ORCPT ); Tue, 6 Jan 2015 17:39:57 -0500 Received: from mail-lb0-f179.google.com ([209.85.217.179]:49625 "EHLO mail-lb0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbbAFWj4 (ORCPT ); Tue, 6 Jan 2015 17:39:56 -0500 Received: by mail-lb0-f179.google.com with SMTP id z11so142528lbi.38 for ; Tue, 06 Jan 2015 14:39:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:mime-version:content-transfer-encoding:content-type; bh=KuqEZ97UyjpJK3qU3mwLOvl4UcVz8VBe3iqdjwio74c=; b=D5+qlkAPv14U+DNVgPboo7+R0CSlGByTil8ikQZ7c3MnRNc5dBum1GoKF2GzUjTNKl JEk2r+JH8lI6z04pTZO++1hpEtzxKSoE1uIdFZ5Xl33lz87CQmH/tBb42rerXN0Ap5XL Q/2vgUnCcoKGxh7inWTtFwzn07+GsWsV8exfqdwsgOYYSAg1J8L9PzqmZ02CBGq4IRMB 6YTaCXU8J4Wve51R7QP5FqIvuOvEmaYcUxMJgkK5BHnNW1+Sl7HP9JCPknboHjKjvHnF o/sSb5RoeeML2V4xLH3nUffa7EYzzdWlbWF7wbPoBYOV2+SjxyGnE0gOgHoQGoD6s70q aEKA== X-Gm-Message-State: ALoCoQksgFVNkmTW4Sn5Izq1mi8gLiv2RFVEn5YV714VWGPJP/LZOsGYDW/6mW/ilISlPuyv58tR X-Received: by 10.152.7.180 with SMTP id k20mr105558511laa.4.1420583994736; Tue, 06 Jan 2015 14:39:54 -0800 (PST) Received: from wasted.cogentembedded.com (ppp83-237-255-190.pppoe.mtu-net.ru. [83.237.255.190]) by mx.google.com with ESMTPSA id wq1sm15660328lbb.24.2015.01.06.14.39.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Jan 2015 14:39:54 -0800 (PST) From: Sergei Shtylyov To: mturquette@linaro.org, linux-kernel@vger.kernel.org, sboyd@codeaurora.org Cc: robh+dt@kernel.org, linux-sh@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org Subject: [PATCH v3 resend] clk-rcar-gen2: ADSP clock support Date: Wed, 07 Jan 2015 01:39:52 +0300 Message-ID: <355163371.fkynKV0U5x@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.3 (Linux/3.17.7-200.fc20.x86_64; KDE/4.14.3; x86_64; ; ) MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov . Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven --- Re-sending with the correct version tag... The patch is against the 'clk-next' branch of Mike Turquette's 'linux.git' repo plus the RCAN clock support patch reposted yesterday. Changes in version 3: - fixed the gated clock register address in cpg_adsp_clk_register(); - moved cpg_adsp_clk_register() and cpg_adsp_div_table[] to be after cpg_rcan_clk_register(); - moved cpg_adsp_clk_register() call after cpg_rcan_clk_register() call; - refreshed the patch. Changes in version 2: - swapped "adsp" and "rcan" in the binding document. Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 5 - drivers/clk/shmobile/clk-rcar-gen2.c | 48 ++++++++++ 2 files changed, 51 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt =================================================================== --- linux.orig/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ linux/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -17,7 +17,8 @@ Required Properties: to the USB_EXTAL clock - #clock-cells: Must be 1 - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", and "rcan" + "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and + "adsp" Example @@ -31,5 +32,5 @@ Example #clock-cells = <1>; clock-output-names = "main", "pll0, "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", - "rcan"; + "rcan", "adsp"; }; Index: linux/drivers/clk/shmobile/clk-rcar-gen2.c =================================================================== --- linux.orig/drivers/clk/shmobile/clk-rcar-gen2.c +++ linux/drivers/clk/shmobile/clk-rcar-gen2.c @@ -33,6 +33,7 @@ struct rcar_gen2_cpg { #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK (0x1f << 8) #define CPG_FRQCRC_ZFC_SHIFT 8 +#define CPG_ADSPCKCR 0x0000025c #define CPG_RCANCKCR 0x00000270 /* ----------------------------------------------------------------------------- @@ -199,6 +200,51 @@ static struct clk * __init cpg_rcan_clk_ return clk; } +/* ADSP divisors */ +static const struct clk_div_table cpg_adsp_div_table[] = { + { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, + { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, + { 10, 36 }, { 11, 48 }, { 0, 0 }, +}; + +static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) +{ + const char *parent_name = "pll1"; + struct clk_divider *div; + struct clk_gate *gate; + struct clk *clk; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + div->reg = cpg->reg + CPG_ADSPCKCR; + div->width = 4; + div->table = cpg_adsp_div_table; + div->lock = &cpg->lock; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(div); + return ERR_PTR(-ENOMEM); + } + + gate->reg = cpg->reg + CPG_ADSPCKCR; + gate->bit_idx = 8; + gate->flags = CLK_GATE_SET_TO_DISABLE; + gate->lock = &cpg->lock; + + clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) { + kfree(gate); + kfree(div); + } + + return clk; +} + /* ----------------------------------------------------------------------------- * CPG Clock Data */ @@ -303,6 +349,8 @@ rcar_gen2_cpg_register_clock(struct devi return cpg_z_clk_register(cpg); } else if (!strcmp(name, "rcan")) { return cpg_rcan_clk_register(cpg, np); + } else if (!strcmp(name, "adsp")) { + return cpg_adsp_clk_register(cpg); } else { return ERR_PTR(-EINVAL); }