| Message ID | 20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | riscv: Support vendor extensions and xtheadvector | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 21 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Apr 15, 2024 at 09:11:59PM -0700, Charlie Jenkins wrote: > The xtheadvector ISA extension is described on the T-Head extension spec > Github page [1] at commit 95358cb2cca9. > > Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 > 35e03d3134b14133f/xtheadvector.adoc [1] This should not be wrapped btw. Otherwise, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..99d2a9e8c52d 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -477,6 +477,10 @@ properties: > latency, as ratified in commit 56ed795 ("Update > riscv-crypto-spec-vector.adoc") of riscv-crypto. > > + # vendor extensions, each extension sorted alphanumerically under the > + # vendor they belong to. Vendors are sorted alphanumerically as well. > + > + # Andes > - const: xandespmu > description: > The Andes Technology performance monitor extension for counter overflow > @@ -484,5 +488,11 @@ properties: > Registers in the AX45MP datasheet. > https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > + # T-HEAD > + - const: xtheadvector > + description: > + The T-HEAD specific 0.7.1 vector implementation as written in > + https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. > + > additionalProperties: true > ... > > -- > 2.44.0 >
On Tue, Apr 16, 2024 at 04:16:30PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:11:59PM -0700, Charlie Jenkins wrote: > > The xtheadvector ISA extension is described on the T-Head extension spec > > Github page [1] at commit 95358cb2cca9. > > > > Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 > > 35e03d3134b14133f/xtheadvector.adoc [1] > > This should not be wrapped btw. > Otherwise, > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> I don't believe it is wrapped? It appears wrapped in your response but it appears on lore correctly: https://lore.kernel.org/lkml/20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com/ - Charlie > > Thanks, > Conor. > > > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 468c646247aa..99d2a9e8c52d 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -477,6 +477,10 @@ properties: > > latency, as ratified in commit 56ed795 ("Update > > riscv-crypto-spec-vector.adoc") of riscv-crypto. > > > > + # vendor extensions, each extension sorted alphanumerically under the > > + # vendor they belong to. Vendors are sorted alphanumerically as well. > > + > > + # Andes > > - const: xandespmu > > description: > > The Andes Technology performance monitor extension for counter overflow > > @@ -484,5 +488,11 @@ properties: > > Registers in the AX45MP datasheet. > > https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > > > + # T-HEAD > > + - const: xtheadvector > > + description: > > + The T-HEAD specific 0.7.1 vector implementation as written in > > + https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. > > + > > additionalProperties: true > > ... > > > > -- > > 2.44.0 > >
On Tue, Apr 16, 2024 at 01:43:06PM -0700, Charlie Jenkins wrote: > On Tue, Apr 16, 2024 at 04:16:30PM +0100, Conor Dooley wrote: > > On Mon, Apr 15, 2024 at 09:11:59PM -0700, Charlie Jenkins wrote: > > > The xtheadvector ISA extension is described on the T-Head extension spec > > > Github page [1] at commit 95358cb2cca9. > > > > > > Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 > > > 35e03d3134b14133f/xtheadvector.adoc [1] > > > > This should not be wrapped btw. > > Otherwise, > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > I don't believe it is wrapped? It appears wrapped in your response but > it appears on lore correctly: > > https://lore.kernel.org/lkml/20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com/ IDK man, looks wrapped on lore too. The other copy of the same link isn't wrapped & I've never had mutt wrap stuff like this before.
On Tue, Apr 16, 2024 at 10:10:39PM +0100, Conor Dooley wrote: > On Tue, Apr 16, 2024 at 01:43:06PM -0700, Charlie Jenkins wrote: > > On Tue, Apr 16, 2024 at 04:16:30PM +0100, Conor Dooley wrote: > > > On Mon, Apr 15, 2024 at 09:11:59PM -0700, Charlie Jenkins wrote: > > > > The xtheadvector ISA extension is described on the T-Head extension spec > > > > Github page [1] at commit 95358cb2cca9. > > > > > > > > Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 > > > > 35e03d3134b14133f/xtheadvector.adoc [1] > > > > > > This should not be wrapped btw. > > > Otherwise, > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > I don't believe it is wrapped? It appears wrapped in your response but > > it appears on lore correctly: > > > > https://lore.kernel.org/lkml/20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com/ > > IDK man, looks wrapped on lore too. The other copy of the same link > isn't wrapped & I've never had mutt wrap stuff like this before. Oops, I was looking at the second one and not the one in the commit message... Thanks. - Charlie
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..99d2a9e8c52d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -477,6 +477,10 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + # vendor extensions, each extension sorted alphanumerically under the + # vendor they belong to. Vendors are sorted alphanumerically as well. + + # Andes - const: xandespmu description: The Andes Technology performance monitor extension for counter overflow @@ -484,5 +488,11 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # T-HEAD + - const: xtheadvector + description: + The T-HEAD specific 0.7.1 vector implementation as written in + https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. + additionalProperties: true ...
The xtheadvector ISA extension is described on the T-Head extension spec Github page [1] at commit 95358cb2cca9. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 35e03d3134b14133f/xtheadvector.adoc [1] Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)