| Message ID | 20240323-8ulp_edma-v3-4-c0e981027c05@nxp.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | dmaengine: fsl-edma: add 8ulp support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On Sat, 23 Mar 2024 11:34:53 -0400, Frank Li wrote: > From: Joy Zou <joy.zou@nxp.com> > > Introduce the compatible string 'fsl,imx8ulp-edma' to enable support for > the i.MX8ULP's eDMA, alongside adjusting the clock numbering. The i.MX8ULP > eDMA architecture features one clock for each DMA channel and an additional > clock for the core controller. Given a maximum of 32 DMA channels, the > maximum clock number consequently increases to 33. > > Signed-off-by: Joy Zou <joy.zou@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Changes in v3: > - Change clock name form CHXX-CLK to chxx > - Fix typeo 'clock' > - Add dma-cell description > - About clock-names: > items: > oneOf: > - const: dma > - pattern: ... > > Which already detect naming wrong, for example: > > clock-names = "dma", "ch00", "ch01", "ch02", "ch03", > .... > "ch28", "ch29", "ch30", "abcc"; > > arch/arm64/boot/dts/freescale/imx8ulp-evk.dtb: dma-controller@29010000: clock-names:32: 'oneOf' conditional failed, one must be fixed: > 'dma' was expected > 'abcc' does not match '^ch(0[0-9]|[1-2][0-9]|3[01])$' > > Only lose order check, such as ch00, dma, ch03, ch02, can pass check. > I think it is good enough. > > I tried rob's suggestion, but met some technology issue. Detail see > > https://lore.kernel.org/imx/20240229-8ulp_edma-v2-0-9d12f883c8f7@nxp.com/T/#mc5767dd505d4b7cfc66586a0631684a57e735476 > > .../devicetree/bindings/dma/fsl,edma.yaml | 40 ++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index aa51d278cb67b..825f4715499e5 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -23,6 +23,7 @@ properties: - fsl,imx7ulp-edma - fsl,imx8qm-adma - fsl,imx8qm-edma + - fsl,imx8ulp-edma - fsl,imx93-edma3 - fsl,imx93-edma4 - fsl,imx95-edma5 @@ -43,6 +44,17 @@ properties: maxItems: 64 "#dma-cells": + description: | + Specifies the number of cells needed to encode an DMA channel. + + Encode for cells number 2: + cell 0: index of dma channel mux instance. + cell 1: peripheral dma request id. + + Encode for cells number 3: + cell 0: peripheral dma request id. + cell 1: dma channel priority. + cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h enum: - 2 - 3 @@ -53,11 +65,11 @@ properties: clocks: minItems: 1 - maxItems: 2 + maxItems: 33 clock-names: minItems: 1 - maxItems: 2 + maxItems: 33 big-endian: description: | @@ -108,6 +120,7 @@ allOf: properties: clocks: minItems: 2 + maxItems: 2 clock-names: items: - const: dmamux0 @@ -136,6 +149,7 @@ allOf: properties: clock: minItems: 2 + maxItems: 2 clock-names: items: - const: dma @@ -151,6 +165,28 @@ allOf: dma-channels: const: 32 + - if: + properties: + compatible: + contains: + const: fsl,imx8ulp-edma + then: + properties: + clocks: + minItems: 33 + clock-names: + minItems: 33 + items: + oneOf: + - const: dma + - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$" + + interrupt-names: false + interrupts: + minItems: 32 + "#dma-cells": + const: 3 + unevaluatedProperties: false examples: