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Fri, 16 Feb 2024 12:33:20 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:7758:12d:16:5f19]) by smtp.gmail.com with ESMTPSA id m5-20020a05600c4f4500b0041253d0acd6sm1420528wmq.47.2024.02.16.12.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 12:33:19 -0800 (PST) From: Bartosz Golaszewski To: Marcel Holtmann , Luiz Augusto von Dentz , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kalle Valo , Bjorn Andersson , Konrad Dybcio , Liam Girdwood , Mark Brown , Catalin Marinas , Will Deacon , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan , Geert Uytterhoeven , Arnd Bergmann , Neil Armstrong , Marek Szyprowski , Alex Elder , Srini Kandagatla , Greg Kroah-Hartman , Abel Vesa , Manivannan Sadhasivam , Lukas Wunner , Dmitry Baryshkov Cc: linux-bluetooth@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-wireless@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 06/18] dt-bindings: new: wireless: describe the ath12k PCI module Date: Fri, 16 Feb 2024 21:32:03 +0100 Message-Id: <20240216203215.40870-7-brgl@bgdev.pl> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240216203215.40870-1-brgl@bgdev.pl> References: <20240216203215.40870-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Add device-tree bindings for the ATH12K module found in the WCN7850 package. Signed-off-by: Bartosz Golaszewski --- .../net/wireless/qcom,ath12k-pci.yaml | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/wireless/qcom,ath12k-pci.yaml diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-pci.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-pci.yaml new file mode 100644 index 000000000000..063c576b99a0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k-pci.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 Linaro Limited +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies ath12k wireless devices (PCIe) + +maintainers: + - Bartosz Golaszewski + +description: | + Qualcomm Technologies IEEE 802.11ax PCIe devices + +properties: + compatible: + enum: + - pci17cb,1107 # WCN7850 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + description: GPIO line enabling the WLAN module + + vdd-supply: + description: VDD supply regulator handle + + vddio-supply: + description: VDD_IO supply regulator handle + + vddio1p2-supply: + description: VDD_IO_1P2 supply regulator handle + + vddaon-supply: + description: VDD_AON supply regulator handle + + vdddig-supply: + description: VDD_DIG supply regulator handle + + vddrfa1p2-supply: + description: VDD_RFA_1P2 supply regulator handle + + vddrfa1p8-supply: + description: VDD_PCIE_1P8 supply regulator handle + + clocks: + maxItems: 1 + description: + Reference clock phandle + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vddaon-supply + - vdddig-supply + - vddrfa1p2-supply + - vddrfa1p8-supply + +additionalProperties: false + +examples: + - | + #include + #include + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bus-range = <0x01 0xff>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>; + + enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + }; + }; + };