| Message ID | 20231116162330.1144983-3-jisheng.teoh@starfivetech.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | StarFive's StarLink PMU Support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Fri, Nov 17, 2023 at 12:23:30AM +0800, Ji Sheng Teoh wrote: > Add device tree binding for StarFive's JH8100 StarLink PMU (Performance > Monitor Unit). > > Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Generally, there's no need to submit new versions so quickly - you can wait for feedback on multiple patches before resubmitting the entire series. Cheers, Conor. > --- > .../perf/starfive,jh8100-starlink-pmu.yaml | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml > new file mode 100644 > index 000000000000..915c6b814026 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml > @@ -0,0 +1,46 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH8100 StarLink PMU > + > +maintainers: > + - Ji Sheng Teoh <jisheng.teoh@starfivetech.com> > + > +description: > + StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a > + shared L3 memory system. The PMU support overflow interrupt, up to > + 16 programmable 64bit event counters, and an independent 64bit cycle > + counter. StarFive's JH8100 StarLink PMU is accessed via MMIO. > + > +properties: > + compatible: > + const: starfive,jh8100-starlink-pmu > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pmu@12900000 { > + compatible = "starfive,jh8100-starlink-pmu"; > + reg = <0x0 0x12900000 0x0 0x10000>; > + interrupts = <34>; > + }; > + }; > -- > 2.25.1 >
On Thu, 16 Nov 2023 17:27:17 +0000 Conor Dooley <conor@kernel.org> wrote: > On Fri, Nov 17, 2023 at 12:23:30AM +0800, Ji Sheng Teoh wrote: > > Add device tree binding for StarFive's JH8100 StarLink PMU > > (Performance Monitor Unit). > > > > Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Generally, there's no need to submit new versions so quickly - you can > wait for feedback on multiple patches before resubmitting the entire > series. > > Cheers, > Conor. > Sure, Thanks for reviewing.
diff --git a/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml new file mode 100644 index 000000000000..915c6b814026 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 StarLink PMU + +maintainers: + - Ji Sheng Teoh <jisheng.teoh@starfivetech.com> + +description: + StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a + shared L3 memory system. The PMU support overflow interrupt, up to + 16 programmable 64bit event counters, and an independent 64bit cycle + counter. StarFive's JH8100 StarLink PMU is accessed via MMIO. + +properties: + compatible: + const: starfive,jh8100-starlink-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmu@12900000 { + compatible = "starfive,jh8100-starlink-pmu"; + reg = <0x0 0x12900000 0x0 0x10000>; + interrupts = <34>; + }; + };
Add device tree binding for StarFive's JH8100 StarLink PMU (Performance Monitor Unit). Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> --- .../perf/starfive,jh8100-starlink-pmu.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml