| Message ID | 20230929084209.3033093-2-quic_ipkumar@quicinc.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Enable USB3 for Qualcomm IPQ5332 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 29/09/2023 10:42, Praveenkumar I wrote: > Document the Qualcomm USB3 22ull UNIPHY present in IPQ5332. > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> > --- > .../bindings/phy/qcom,ipq5332-usb-uniphy.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml Filename should match compatible. > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml > new file mode 100644 > index 000000000000..90434cee9cdd > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-uniphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm USB Super-Speed UNIPHY > + > +maintainers: > + - Praveenkumar I <quic_ipkumar@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.com> > + > +description: > + USB Super-Speed UNIPHY found in Qualcomm IPQ5332, IPQ5018 SoCs. > + > +properties: > + compatible: > + items: Drop items, not needed. > + - const: qcom,ipq5332-usb-ssphy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 3 > + > + clock-names: > + items: > + - const: ahb > + - const: cfg_ahb > + - const: pipe > + > + resets: > + maxItems: 1 > + > + vdd-supply: > + description: > + Phandle to 5V regulator supply to PHY digital circuit. > + > + qcom,phy-usb-mux-sel: > + description: PHY Mux Selection for USB > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle of TCSR syscon > + - description: offset of PHY Mux selection register > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 You miss required: block. Best regards, Krzysztof
On 9/30/2023 8:26 PM, Krzysztof Kozlowski wrote: > On 29/09/2023 10:42, Praveenkumar I wrote: >> Document the Qualcomm USB3 22ull UNIPHY present in IPQ5332. >> >> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> >> --- >> .../bindings/phy/qcom,ipq5332-usb-uniphy.yaml | 83 +++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml > Filename should match compatible. Will address it. > >> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml >> new file mode 100644 >> index 000000000000..90434cee9cdd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-uniphy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm USB Super-Speed UNIPHY >> + >> +maintainers: >> + - Praveenkumar I <quic_ipkumar@quicinc.com> >> + - Varadarajan Narayanan <quic_varada@quicinc.com> >> + >> +description: >> + USB Super-Speed UNIPHY found in Qualcomm IPQ5332, IPQ5018 SoCs. >> + >> +properties: >> + compatible: >> + items: > Drop items, not needed. Sure, will drop. > >> + - const: qcom,ipq5332-usb-ssphy >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 3 >> + >> + clock-names: >> + items: >> + - const: ahb >> + - const: cfg_ahb >> + - const: pipe >> + >> + resets: >> + maxItems: 1 >> + >> + vdd-supply: >> + description: >> + Phandle to 5V regulator supply to PHY digital circuit. >> + >> + qcom,phy-usb-mux-sel: >> + description: PHY Mux Selection for USB >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle of TCSR syscon >> + - description: offset of PHY Mux selection register >> + >> + "#clock-cells": >> + const: 0 >> + >> + clock-output-names: >> + maxItems: 1 >> + >> + "#phy-cells": >> + const: 0 > You miss required: block. Sure, will add. -- Thanks, Praveenkumar > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml new file mode 100644 index 000000000000..90434cee9cdd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-uniphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm USB Super-Speed UNIPHY + +maintainers: + - Praveenkumar I <quic_ipkumar@quicinc.com> + - Varadarajan Narayanan <quic_varada@quicinc.com> + +description: + USB Super-Speed UNIPHY found in Qualcomm IPQ5332, IPQ5018 SoCs. + +properties: + compatible: + items: + - const: qcom,ipq5332-usb-ssphy + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: ahb + - const: cfg_ahb + - const: pipe + + resets: + maxItems: 1 + + vdd-supply: + description: + Phandle to 5V regulator supply to PHY digital circuit. + + qcom,phy-usb-mux-sel: + description: PHY Mux Selection for USB + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of PHY Mux selection register + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + usb-phy@4b0000 { + compatible = "qcom,ipq5332-usb-uniphy"; + reg = <0x4b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "ahb", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk_src"; + + #phy-cells = <0>; + + qcom,phy-usb-mux-sel = <&tcsr 0x10540>; + + vdd-supply = <®ulator_fixed_5p0>; + };
Document the Qualcomm USB3 22ull UNIPHY present in IPQ5332. Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> --- .../bindings/phy/qcom,ipq5332-usb-uniphy.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-uniphy.yaml