| Message ID | 20230628-topic-a7xx_drmmsm-v1-1-a7f4496e0c12@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | A7xx support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On 28/06/2023 22:35, Konrad Dybcio wrote: > The GMU on the A7xx series is pretty much the same as on the A6xx parts. > It's now "smarter", needs a bit less register writes and controls more > things (like inter-frame power collapse) mostly internally (instead of > us having to write to G[PM]U_[CG]X registers from APPS) > > The only difference worth mentioning is the now-required DEMET clock, > which is strictly required for things like asserting reset lines, not > turning it on results in GMU not being fully functional (all OOB requests > would fail and HFI would hang after the first submitted OOB). > > Describe the A730 and A740 GMU. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 5fc4106110ad..20ddb89a4500 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -21,7 +21,7 @@ properties: compatible: oneOf: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - const: qcom,adreno-gmu-wrapper @@ -213,6 +213,44 @@ allOf: - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-730.1 + - qcom,adreno-gmu-740.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GPUSS DEMET clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - const: demet + - if: properties: compatible:
The GMU on the A7xx series is pretty much the same as on the A6xx parts. It's now "smarter", needs a bit less register writes and controls more things (like inter-frame power collapse) mostly internally (instead of us having to write to G[PM]U_[CG]X registers from APPS) The only difference worth mentioning is the now-required DEMET clock, which is strictly required for things like asserting reset lines, not turning it on results in GMU not being fully functional (all OOB requests would fail and HFI would hang after the first submitted OOB). Describe the A730 and A740 GMU. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../devicetree/bindings/display/msm/gmu.yaml | 40 +++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-)