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[v2] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4

Message ID 20230127140446.1728102-1-yoshihiro.shimoda.uh@renesas.com
State Changes Requested, archived
Headers show
Series [v2] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4 | expand

Checks

Context Check Description
robh/checkpatch success
robh/patch-applied success
robh/dtbs-check warning build log
robh/dt-meta-schema success

Commit Message

Yoshihiro Shimoda Jan. 27, 2023, 2:04 p.m. UTC
Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, update
the renesas,ipmmu-main property which allows to only set the first
argument for R-Car Gen4.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Changes from v1:
https://lore.kernel.org/all/20230123012940.1250879-1-yoshihiro.shimoda.uh@renesas.com/
 - Change number of argument for R-Car Gen4 instead of "module id".
   On the discussion, using 'minItems' is a solution. But, it causes
   "too short" errors on dtbs_check. So, using "oneOf" instead.

 .../bindings/iommu/renesas,ipmmu-vmsa.yaml         | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

Comments

Rob Herring (Arm) Jan. 30, 2023, 7:37 p.m. UTC | #1
On Fri, Jan 27, 2023 at 11:04:46PM +0900, Yoshihiro Shimoda wrote:
> Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, update
> the renesas,ipmmu-main property which allows to only set the first
> argument for R-Car Gen4.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> Changes from v1:
> https://lore.kernel.org/all/20230123012940.1250879-1-yoshihiro.shimoda.uh@renesas.com/
>  - Change number of argument for R-Car Gen4 instead of "module id".
>    On the discussion, using 'minItems' is a solution. But, it causes
>    "too short" errors on dtbs_check. So, using "oneOf" instead.

What was the schema you had?


I've commented on v1.

Rob
Yoshihiro Shimoda Jan. 31, 2023, 5:59 a.m. UTC | #2
> From: Rob Herring, Sent: Tuesday, January 31, 2023 4:37 AM
> 
> On Fri, Jan 27, 2023 at 11:04:46PM +0900, Yoshihiro Shimoda wrote:
> > Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, update
> > the renesas,ipmmu-main property which allows to only set the first
> > argument for R-Car Gen4.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > Changes from v1:
> >
<snip the URL>
> >  - Change number of argument for R-Car Gen4 instead of "module id".
> >    On the discussion, using 'minItems' is a solution. But, it causes
> >    "too short" errors on dtbs_check. So, using "oneOf" instead.
> 
> What was the schema you had?

I added "minItems: 1" like below:
---
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -74,6 +74,7 @@ properties:
   renesas,ipmmu-main:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     items:
+      - minItems: 1
       - items:
           - description: phandle to main IPMMU
           - description: the interrupt bit number associated with the particular
---

But, a lot of following errors happened on dtbs_check.
---
  DTC_CHK arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dtb
/home/shimoda/development/linux/worktrees/iommu/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dtb: iommu@e6740000: renesas,ipmmu-main:1: [0] is too short
        From schema: /home/shimoda/development/linux/worktrees/iommu/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
---

If I modified the file like below, the error disappeared.
But, this is not matched with the commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), I think.
---
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -73,12 +73,12 @@ properties:

   renesas,ipmmu-main:
     $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
     items:
-      - items:
-          - description: phandle to main IPMMU
-          - description: the interrupt bit number associated with the particular
-              cache IPMMU device. The interrupt bit number needs to match the main
-              IPMMU IMSSTR register. Only used by cache IPMMU instances.
+      - description: phandle to main IPMMU
+      - description: the interrupt bit number associated with the particular
+          cache IPMMU device. The interrupt bit number needs to match the main
+          IPMMU IMSSTR register. Only used by cache IPMMU instances.
     description:
       Reference to the main IPMMU phandle plus 1 cell. The cell is
       the interrupt bit number associated with the particular cache IPMMU
---

Best regards,
Yoshihiro Shimoda

> I've commented on v1.

Thank you for your comment on v1!

Best regards,
Yoshihiro Shimoda

> Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
index 72308a4c14e7..8e8f79f612e5 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -73,12 +73,16 @@  properties:
 
   renesas,ipmmu-main:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
+    oneOf:
+      - items:
+          - items:
+              - description: phandle to main IPMMU
+              - description: the interrupt bit number associated with the particular
+                  cache IPMMU device. The interrupt bit number needs to match the main
+                  IPMMU IMSSTR register. Only used by cache IPMMU instances.
       - items:
-          - description: phandle to main IPMMU
-          - description: the interrupt bit number associated with the particular
-              cache IPMMU device. The interrupt bit number needs to match the main
-              IPMMU IMSSTR register. Only used by cache IPMMU instances.
+          - items:
+              - description: phandle to main IPMMU
     description:
       Reference to the main IPMMU phandle plus 1 cell. The cell is
       the interrupt bit number associated with the particular cache IPMMU