| Message ID | 20221211024859.672076-1-marex@denx.de |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v6,1/3] dt-bindings: imx6q-pcie: Handle various clock configurations | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On Sun, Dec 11, 2022 at 03:48:57AM +0100, Marek Vasut wrote: > The i.MX SoCs have various clock configurations routed into the PCIe IP, > the list of clock is below. Document all those configurations in the DT > binding document. > > All SoCs: pcie, pcie_bus > 6QDL, 7D: + pcie_phy > 6SX: + pcie_phy pcie_inbound_axi > 8MQ: + pcie_phy pcie_aux > 8MM, 8MP: + pcie_aux > > Reviewed-by: Rob Herring <robh@kernel.org> > Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com> > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: NXP Linux Team <linux-imx@nxp.com> > To: devicetree@vger.kernel.org > --- > V2: - Add AB from Alex > V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles > - Flatten the if-else structure > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected > V4: - Reinstate minItems: for clock-names in main section, turn the > last two clock-names items into enums to cover all IP variants. > - Add another allOf entry for mx6q/mx6qp/mx7d clock-names list. > - Adjust clock maxItems in the allOf section. > V5: - No change > V6: - Add RB from Rob This should have also gone to PCI maintainers and list so they could pick it up. However, I'll apply the series. Rob
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 49b4f7a32e71e..bfb9502d9fc0b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -57,8 +57,8 @@ properties: items: - const: pcie - const: pcie_bus - - const: pcie_phy - - enum: [ pcie_inbound_axi, pcie_aux ] + - enum: [ pcie_phy, pcie_aux ] + - enum: [ pcie_aux, pcie_inbound_axi ] num-lanes: const: 1 @@ -215,6 +215,72 @@ allOf: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + + - if: + properties: + compatible: + contains: + const: fsl,imx6sx-pcie + then: + properties: + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_inbound_axi + + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-pcie + then: + properties: + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_aux + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_aux + examples: - | #include <dt-bindings/clock/imx6qdl-clock.h>