| Message ID | 20220926132114.60396-5-biju.das.jz@bp.renesas.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add RZ/G2L MTU3a MFD and Counter driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 26/09/2022 15:21, Biju Das wrote: > Document 16-bit and 32-bit phase counting mode support on > RZ/G2L MTU3 IP. > Squash with previous. New devices are added complete, not artificially split into multiple non-working components. > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > index c1fae8e8d9f9..c4bcf28623d6 100644 > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > @@ -192,6 +192,37 @@ properties: > "#size-cells": > const: 0 > > +patternProperties: > + "^counter@[1-2]+$": > + type: object additionalProperties: false > + > + properties: > + compatible: > + const: renesas,rzg2l-mtu3-counter > + > + reg: > + description: Identify counter channels. > + items: > + enum: [ 1, 2 ] > + > + renesas,32bit-phase-counting: > + type: boolean > + description: Enable 32-bit phase counting mode. > + > + renesas,ext-input-phase-clock-select: I propose to drop "input". I understand you just select pins with clock? If it is external clock, then why not using generic clock bindings? > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + default: 1 > + description: | > + Selects the external clock pin for phase counting mode. > + <0> : MTCLKA and MTCLKB are selected for the external phase clock. > + <1> : MTCLKC and MTCLKD are selected for the external phase clock > + (default) > + > + required: > + - compatible > + - reg > + > required: > - compatible > - reg > @@ -270,6 +301,10 @@ examples: > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > power-domains = <&cpg>; > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; Blank line > + counter@1 { > + compatible = "renesas,rzg2l-mtu3-counter"; > + reg = <1>; > + }; > }; > > ... Best regards, Krzysztof
Hi Krzysztof Kozlowski, > Subject: Re: [PATCH RFC 4/8] dt-bindings: mfd: rzg2l-mtu3: Document > RZ/G2UL MTU3 counter > > On 26/09/2022 15:21, Biju Das wrote: > > Document 16-bit and 32-bit phase counting mode support on RZ/G2L > MTU3 > > IP. > > > > Squash with previous. New devices are added complete, not artificially > split into multiple non-working components. Ok will squash into previous patch. > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 > +++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > index c1fae8e8d9f9..c4bcf28623d6 100644 > > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > @@ -192,6 +192,37 @@ properties: > > "#size-cells": > > const: 0 > > > > +patternProperties: > > + "^counter@[1-2]+$": > > + type: object > > additionalProperties: false OK. > > > + > > + properties: > > + compatible: > > + const: renesas,rzg2l-mtu3-counter > > + > > + reg: > > + description: Identify counter channels. > > + items: > > + enum: [ 1, 2 ] > > + > > + renesas,32bit-phase-counting: > > + type: boolean > > + description: Enable 32-bit phase counting mode. > > + > > + renesas,ext-input-phase-clock-select: > > I propose to drop "input". I understand you just select pins with > clock? > If it is external clock, then why not using generic clock bindings? It is basically clock pins as discussed in [1], There will be a new sysfs in counter subsytem for handling this. Hardware supports 4 pins for phase counting mode, MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1/MTU2 phase counting mode B phase input) MTCLKC Input External clock C input pin (MTU2 phase counting mode A phase input) MTCLKD Input External clock D input pin (MTU2 phase counting mode B phase input) For MTU1, it is fixed MTCLKA and MTCLKB. But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - { MTCLKC , MTCLKD} On reset it is set to { MTCLKC , MTCLKD}. [1] https://lore.kernel.org/linux-renesas-soc/OS0PR01MB59223F69EA3215528519F49086599@OS0PR01MB5922.jpnprd01.prod.outlook.com/T/#mb7db950c9eb61ac52f405cdc654a409b8cb198f9 As per [1], it is going to be modelled as , if everyone ok with it. counter: type: object properties: compatible: const: renesas,rzg2l-mtu3-counter > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [ 0, 1 ] > > + default: 1 > > + description: | > > + Selects the external clock pin for phase counting mode. > > + <0> : MTCLKA and MTCLKB are selected for the external > phase clock. > > + <1> : MTCLKC and MTCLKD are selected for the external > phase clock > > + (default) > > + > > + required: > > + - compatible > > + - reg > > + > > required: > > - compatible > > - reg > > @@ -270,6 +301,10 @@ examples: > > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > > power-domains = <&cpg>; > > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > > Blank line OK will fix it. Cheers, Biju > > > + counter@1 { > > + compatible = "renesas,rzg2l-mtu3-counter"; > > + reg = <1>; > > + }; > > }; > > > > ... > > Best regards, > Krzysztof
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml index c1fae8e8d9f9..c4bcf28623d6 100644 --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml @@ -192,6 +192,37 @@ properties: "#size-cells": const: 0 +patternProperties: + "^counter@[1-2]+$": + type: object + + properties: + compatible: + const: renesas,rzg2l-mtu3-counter + + reg: + description: Identify counter channels. + items: + enum: [ 1, 2 ] + + renesas,32bit-phase-counting: + type: boolean + description: Enable 32-bit phase counting mode. + + renesas,ext-input-phase-clock-select: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + default: 1 + description: | + Selects the external clock pin for phase counting mode. + <0> : MTCLKA and MTCLKB are selected for the external phase clock. + <1> : MTCLKC and MTCLKD are selected for the external phase clock + (default) + + required: + - compatible + - reg + required: - compatible - reg @@ -270,6 +301,10 @@ examples: clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; + counter@1 { + compatible = "renesas,rzg2l-mtu3-counter"; + reg = <1>; + }; }; ...
Document 16-bit and 32-bit phase counting mode support on RZ/G2L MTU3 IP. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)