[v2,1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name Composable cache to prevent confusion.

Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Suggested-by: Ben Dooks <ben.dooks@sifive.com>
---
 ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
 1 file changed, 23 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Since composable cache may be L3 cache if private L2 cache exists, we
> should use its original name Composable cache to prevent confusion.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>

LGTM, thanks for fixing up the patch to actually show the move.
Not sure if the DT guys will want the move and the extra compatible
to be in extra patches, but to me it seems fair enough to do it all
in one go.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>  1 file changed, 23 insertions(+), 5 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> similarity index 83%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> index ca3b9be58058..bf3f07421f7e 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> @@ -2,18 +2,18 @@
>  # Copyright (C) 2020 SiFive, Inc.
>  %YAML 1.2
>  ---
> -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
> +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
> 
> -title: SiFive L2 Cache Controller
> +title: SiFive Composable Cache Controller
> 
>  maintainers:
>    - Sagar Kadam <sagar.kadam@sifive.com>
>    - Paul Walmsley  <paul.walmsley@sifive.com>
> 
>  description:
> -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> +  The SiFive Composable Cache Controller is used to provide access to fast copies
> +  of memory for masters in a Core Complex. The Composable Cache Controller also
>    acts as directory-based coherency manager.
>    All the properties in ePAPR/DeviceTree specification applies for this platform.
> 
> @@ -22,6 +22,7 @@ select:
>      compatible:
>        contains:
>          enum:
> +          - sifive,ccache0
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> 
> @@ -33,6 +34,7 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> +              - sifive,ccache0
>                - sifive,fu540-c000-ccache
>                - sifive,fu740-c000-ccache
>            - const: cache
> @@ -45,7 +47,7 @@ properties:
>      const: 64
> 
>    cache-level:
> -    const: 2
> +    enum: [2, 3]
> 
>    cache-sets:
>      enum: [1024, 2048]
> @@ -115,6 +117,22 @@ allOf:
>          cache-sets:
>            const: 1024
> 
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: sifive,ccache0
> +
> +    then:
> +      properties:
> +        cache-level:
> +          enum: [2, 3]
> +
> +    else:
> +      properties:
> +        cache-level:
> +          const: 2
> +
>  additionalProperties: false
> 
>  required:
> --
> 2.17.1
>

On Mon, 05 Sep 2022 08:31:20 +0000, Zong Li wrote:
> Since composable cache may be L3 cache if private L2 cache exists, we
> should use its original name Composable cache to prevent confusion.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>  1 file changed, 23 insertions(+), 5 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

On 08/09/2022 22:21, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 05 Sep 2022 08:31:20 +0000, Zong Li wrote:
>> Since composable cache may be L3 cache if private L2 cache exists, we
>> should use its original name Composable cache to prevent confusion.
>>
>> Signed-off-by: Zong Li <zong.li@sifive.com>
>> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
>> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
>> ---
>>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>>  1 file changed, 23 insertions(+), 5 deletions(-)
>>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
>>
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

FWIW this was respun today:
https://lore.kernel.org/linux-riscv/20220908144424.4232-1-zong.li@sifive.com/

Content of this patch should be no different.