| Message ID | 20211221094717.16187-12-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add new Renesas RZ/V2L SoC and Renesas RZ/V2L SMARC EVK support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dtbs-check | success | |
| robh/dt-meta-schema | fail | build log |
On Tue, 21 Dec 2021 09:47:12 +0000, Lad Prabhakar wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L is package- and > pin-compatible with the RZ/G2L. No driver changes are required as RZ/G2L > compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml:26:13: [warning] wrong indentation: expected 14 but found 12 (indentation) dtschema/dtc warnings/errors: doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1571555 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Tue, 21 Dec 2021 09:47:12 +0000, Lad Prabhakar wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L is package- and > pin-compatible with the RZ/G2L. No driver changes are required as RZ/G2L > compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > With the indentation fixed: Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index ef68dabcf4dc..2b4a53600333 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1