| Message ID | 20210901131049.1365367-2-tanmay@marvell.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | coresight: tmc: Add support to configure AXI burst size | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@marvell.com> wrote: > > Add "arm,max-burst-size" optional property for TMC ETR. > If specified, this value indicates the maximum burst size > that can be initiated by TMC on the AXI bus. > > Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> > --- > Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index 7f9c1ca87487..7971f8dba2ee 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -127,6 +127,11 @@ its hardware characteristcs. > * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely > use the SG mode on this system. > > + * arm,max-burst-size: The maximum burst size initiated by TMC on the > + AXI master interface. The burst size can be in the range [0..15], > + the setting supports one data transfer per burst upto a maximum of > + 16 data transfers per burst. > + > * Optional property for CATU : > * interrupts : Exactly one SPI may be listed for reporting the address > error > -- > 2.25.1 > Reviewed-by: Mike Leach <mike.leach@linaro.org>
On Wed, 01 Sep 2021 18:40:48 +0530, Tanmay Jagdale wrote: > Add "arm,max-burst-size" optional property for TMC ETR. > If specified, this value indicates the maximum burst size > that can be initiated by TMC on the AXI bus. > > Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> > --- > Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++ > 1 file changed, 5 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 7f9c1ca87487..7971f8dba2ee 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -127,6 +127,11 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * arm,max-burst-size: The maximum burst size initiated by TMC on the + AXI master interface. The burst size can be in the range [0..15], + the setting supports one data transfer per burst upto a maximum of + 16 data transfers per burst. + * Optional property for CATU : * interrupts : Exactly one SPI may be listed for reporting the address error
Add "arm,max-burst-size" optional property for TMC ETR. If specified, this value indicates the maximum burst size that can be initiated by TMC on the AXI bus. Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> --- Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++ 1 file changed, 5 insertions(+)