| Message ID | 20210222112314.10772-2-kishon@ti.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | AM64: Add SERDES bindings and driver support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success | |
| robh/dtbs-check | success |
Hi Rob, On 22/02/21 4:53 pm, Kishon Vijay Abraham I wrote: > Add bindings for AM64 SERDES Wrapper. I've fixed all your comments provided in the previous version. Can you review this and give your ACKs please? Best Regards, Kishon > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 ++++++--- > include/dt-bindings/phy/phy-ti.h | 21 +++++++++++++++++++ > 2 files changed, 28 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/phy/phy-ti.h > > diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > index c33e9bc79521..bf431f98e6ea 100644 > --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > @@ -12,9 +12,10 @@ maintainers: > > properties: > compatible: > - enum: > - - ti,j721e-wiz-16g > - - ti,j721e-wiz-10g > + oneOf: > + - const: ti,j721e-wiz-16g > + - const: ti,j721e-wiz-10g > + - const: ti,am64-wiz-10g > > power-domains: > maxItems: 1 > @@ -42,6 +43,9 @@ properties: > "#reset-cells": > const: 1 > > + "#clock-cells": > + const: 1 > + > ranges: true > > assigned-clocks: > diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h > new file mode 100644 > index 000000000000..ad955d3a56b4 > --- /dev/null > +++ b/include/dt-bindings/phy/phy-ti.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * This header provides constants for TI SERDES. > + */ > + > +#ifndef _DT_BINDINGS_TI_SERDES > +#define _DT_BINDINGS_TI_SERDES > + > +/* Clock index for output clocks from WIZ */ > + > +/* MUX Clocks */ > +#define TI_WIZ_PLL0_REFCLK 0 > +#define TI_WIZ_PLL1_REFCLK 1 > +#define TI_WIZ_REFCLK_DIG 2 > + > +/* Reserve index here for future additions */ > + > +/* MISC Clocks */ > +#define TI_WIZ_PHY_EN_REFCLK 16 > + > +#endif /* _DT_BINDINGS_TI_SERDES */ >
On Mon, Feb 22, 2021 at 04:53:06PM +0530, Kishon Vijay Abraham I wrote: > Add bindings for AM64 SERDES Wrapper. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 ++++++--- > include/dt-bindings/phy/phy-ti.h | 21 +++++++++++++++++++ > 2 files changed, 28 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/phy/phy-ti.h > > diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > index c33e9bc79521..bf431f98e6ea 100644 > --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml > @@ -12,9 +12,10 @@ maintainers: > > properties: > compatible: > - enum: > - - ti,j721e-wiz-16g > - - ti,j721e-wiz-10g > + oneOf: > + - const: ti,j721e-wiz-16g > + - const: ti,j721e-wiz-10g > + - const: ti,am64-wiz-10g Why do you need to change this from an enum? > > power-domains: > maxItems: 1 > @@ -42,6 +43,9 @@ properties: > "#reset-cells": > const: 1 > > + "#clock-cells": > + const: 1 > + > ranges: true > > assigned-clocks: > diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h > new file mode 100644 > index 000000000000..ad955d3a56b4 > --- /dev/null > +++ b/include/dt-bindings/phy/phy-ti.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * This header provides constants for TI SERDES. > + */ > + > +#ifndef _DT_BINDINGS_TI_SERDES > +#define _DT_BINDINGS_TI_SERDES > + > +/* Clock index for output clocks from WIZ */ > + > +/* MUX Clocks */ > +#define TI_WIZ_PLL0_REFCLK 0 > +#define TI_WIZ_PLL1_REFCLK 1 > +#define TI_WIZ_REFCLK_DIG 2 > + > +/* Reserve index here for future additions */ > + > +/* MISC Clocks */ > +#define TI_WIZ_PHY_EN_REFCLK 16 > + > +#endif /* _DT_BINDINGS_TI_SERDES */ > -- > 2.17.1 >
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index c33e9bc79521..bf431f98e6ea 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -12,9 +12,10 @@ maintainers: properties: compatible: - enum: - - ti,j721e-wiz-16g - - ti,j721e-wiz-10g + oneOf: + - const: ti,j721e-wiz-16g + - const: ti,j721e-wiz-10g + - const: ti,am64-wiz-10g power-domains: maxItems: 1 @@ -42,6 +43,9 @@ properties: "#reset-cells": const: 1 + "#clock-cells": + const: 1 + ranges: true assigned-clocks: diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h new file mode 100644 index 000000000000..ad955d3a56b4 --- /dev/null +++ b/include/dt-bindings/phy/phy-ti.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI SERDES. + */ + +#ifndef _DT_BINDINGS_TI_SERDES +#define _DT_BINDINGS_TI_SERDES + +/* Clock index for output clocks from WIZ */ + +/* MUX Clocks */ +#define TI_WIZ_PLL0_REFCLK 0 +#define TI_WIZ_PLL1_REFCLK 1 +#define TI_WIZ_REFCLK_DIG 2 + +/* Reserve index here for future additions */ + +/* MISC Clocks */ +#define TI_WIZ_PHY_EN_REFCLK 16 + +#endif /* _DT_BINDINGS_TI_SERDES */
Add bindings for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 ++++++--- include/dt-bindings/phy/phy-ti.h | 21 +++++++++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/phy/phy-ti.h