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[v1,6/9] dt-bindings: mmc: Update phy and regulator supply for Keem Bay SOC

Message ID 20210114152700.21916-7-muhammad.husaini.zulkifli@intel.com
State Changes Requested
Headers show
Series mmc: sdhci-of-arasan: Add UHS-1 support for Keem Bay SOC | expand


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Commit Message

Muhammad Husaini Zulkifli Jan. 14, 2021, 3:26 p.m. UTC
Add DT bindings of vmmc, vqmmc and sdvrail supplies of regulator
and phys for the phandle of sd0_phy which contain additional property
for otap delay and sel_clk_buffer.

Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
diff mbox series


diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
index 37a5fe7b26dc..b77a1ff37afa 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
@@ -83,7 +83,7 @@  properties:
       - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
           For this device it is strongly suggested to include
-          arasan,soc-ctl-syscon.
+          arasan,soc-ctl-syscon, phys, vmmc-supply, vqmmc-supply and sdvrail-supply.
       - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
           For this device it is strongly suggested to include
@@ -299,5 +299,10 @@  examples:
           clock-names = "clk_xin", "clk_ahb";
           clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
                    <&scmi_clk KEEM_BAY_PSS_SD0>;
+          phys = <&sd0_phy>;
+          phy-names = "phy_arasan";
           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+          vmmc-supply = <&reg_sd0_vcc>;
+          vqmmc-supply = <&reg_sd0_vqcc>;
+          sdvrail-supply = <&regulator_rail>;