Message ID | 20210114101949.23859-2-amelie.delaunay@foss.st.com |
---|---|
State | Superseded, archived |
Headers | show |
Series | STM32 USBPHYC ck_usbo_48m clock provider | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success |
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 46df6786727a..4e4da64b8e01 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -51,6 +51,10 @@ properties: vdda1v8-supply: description: regulator providing 1V8 power supply to the PLL block + '#clock-cells': + description: number of clock cells for ck_usbo_48m consumer + const: 0 + #Required child nodes: patternProperties: @@ -102,6 +106,7 @@ required: - "#size-cells" - vdda1v1-supply - vdda1v8-supply + - '#clock-cells' - usb-phy@0 - usb-phy@1 @@ -120,6 +125,7 @@ examples: vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>;
usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 6 ++++++ 1 file changed, 6 insertions(+)