Message ID | 20210104124103.30930-4-kishon@ti.com |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | AM64: Add PCIe bindings and driver support | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success | |
robh/checkpatch | success | |
robh/dt-meta-schema | success | |
robh/dtbs-check | fail | build log |
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index d06f0c4464c6..447c8fe0f09e 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -16,12 +16,17 @@ allOf: properties: compatible: oneOf: - - description: PCIe EP controller in J7200 + - const: ti,am64-pcie-ep + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in AM64 items: + - const: ti,am64-pcie-ep - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep - - description: PCIe EP controller in J721E + - description: PCIe EP controller in J7200 items: + - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep reg: @@ -66,7 +71,6 @@ required: - power-domains - clocks - clock-names - - dma-coherent - max-functions - phys - phy-names
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)