diff mbox series

[v4,1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

Message ID 20201207090013.14145-1-troy_lee@aspeedtech.com
State Not Applicable, archived
Headers show
Series [v4,1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support | expand

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Context Check Description
robh/checkpatch success

Commit Message

Troy Lee Dec. 7, 2020, 9 a.m. UTC
Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Acked-by: Joel Stanley <joel@jms.id.au>
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt       | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Stefan Schaeckeler (sschaeck) Dec. 7, 2020, 9:10 a.m. UTC | #1
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com>


> ---
     drivers/edac/Kconfig       | 6 +++---
>  drivers/edac/aspeed_edac.c | 7 +++++--
>  2 files changed, 8 insertions(+), 5 deletions(-)

> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 7a47680d6f07..c410331e8ee8 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -515,10 +515,10 @@ config EDAC_QCOM
>  	  health, you should probably say 'Y' here.
>
>  config EDAC_ASPEED
> -	tristate "Aspeed AST 2500 SoC"
> -	depends on MACH_ASPEED_G5
> +	tristate "Aspeed AST BMC SoC"
> +	depends on ARCH_ASPEED
>  	help
> -	  Support for error detection and correction on the Aspeed AST 2500 SoC.
> +	  Support for error detection and correction on the Aspeed AST BMC SoC.
>
>  	  First, ECC must be configured in the bootloader. Then, this driver
>  	  will expose error counters via the EDAC kernel framework.
> diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> index fde809efc520..a46da56d6d54 100644
> --- a/drivers/edac/aspeed_edac.c
> +++ b/drivers/edac/aspeed_edac.c
> @@ -239,7 +239,7 @@ static int init_csrows(struct mem_ctl_info *mci)
>  	int rc;
>
>  	/* retrieve info about physical memory from device tree */
> -	np = of_find_node_by_path("/memory");
> +	np = of_find_node_by_name(NULL, "memory");
>  	if (!np) {
>  		dev_err(mci->pdev, "dt: missing /memory node\n");
>  		return -ENODEV;
> @@ -375,10 +375,13 @@ static int aspeed_remove(struct platform_device *pdev)
>
>
>  static const struct of_device_id aspeed_of_match[] = {
> +	{ .compatible = "aspeed,ast2400-sdram-edac" },
>  	{ .compatible = "aspeed,ast2500-sdram-edac" },
> +	{ .compatible = "aspeed,ast2600-sdram-edac" },
>  	{},
>  };
>
> +MODULE_DEVICE_TABLE(of, aspeed_of_match);
>
>  static struct platform_driver aspeed_driver = {
>  	.driver		= {
> @@ -392,5 +395,5 @@ module_platform_driver(aspeed_driver);
>
>  MODULE_LICENSE("GPL");
>  MODULE_AUTHOR("Stefan Schaeckeler <sschaeck@cisco.com>");
> -MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
> +MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver");
>  MODULE_VERSION("1.0");
> -- 
> 2.17.1
Borislav Petkov Dec. 7, 2020, 11:11 a.m. UTC | #2
On Mon, Dec 07, 2020 at 05:00:11PM +0800, Troy Lee wrote:
> Adding Aspeed AST2400 and AST2600 binding for edac driver.
> 
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Acked-by: Joel Stanley <joel@jms.id.au>
> ---
>  .../devicetree/bindings/edac/aspeed-sdram-edac.txt       | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)

All 3 applied, thanks.
Joel Stanley Dec. 7, 2020, 11:53 a.m. UTC | #3
On Mon, 7 Dec 2020 at 09:01, Troy Lee <troy_lee@aspeedtech.com> wrote:
>
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@ 
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@  Note, the bootloader must configure ECC mode in the memory controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+	- "aspeed,ast2400-sdram-edac"
+	- "aspeed,ast2500-sdram-edac"
+	- "aspeed,ast2600-sdram-edac"
 - reg:        sdram controller register set should be <0x1e6e0000 0x174>
 - interrupts: should be AVIC interrupt #0