From patchwork Mon Nov 16 16:24:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1401030 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CZZDc4l8Dz9sSn for ; Tue, 17 Nov 2020 03:25:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731972AbgKPQYh (ORCPT ); Mon, 16 Nov 2020 11:24:37 -0500 Received: from relay11.mail.gandi.net ([217.70.178.231]:38341 "EHLO relay11.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731960AbgKPQYg (ORCPT ); Mon, 16 Nov 2020 11:24:36 -0500 Received: from localhost (91-175-115-186.subs.proxad.net [91.175.115.186]) (Authenticated sender: gregory.clement@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id 56ED1100002; Mon, 16 Nov 2020 16:24:33 +0000 (UTC) From: Gregory CLEMENT To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Cc: Thomas Petazzoni , Alexandre Belloni , Lars Povlsen , , Gregory CLEMENT Subject: [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Date: Mon, 16 Nov 2020 17:24:24 +0100 Message-Id: <20201116162427.1727851-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201116162427.1727851-1-gregory.clement@bootlin.com> References: <20201116162427.1727851-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the Device Tree binding documentation for the Microsemi Jaguar2, Luton and Serval interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT --- .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index 3a537635a859..5483ed7062ba 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -21,7 +21,11 @@ properties: compatible: items: - enum: + - mscc,jaguar2-icpu-intr + - mscc,luton-icpu-intr - mscc,ocelot-icpu-intr + - mscc,serval-icpu-intr + '#interrupt-cells': const: 1