| Message ID | 20201107081420.60325-25-damien.lemoal@wdc.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | RISC-V Kendryte K210 support improvments | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On 11/7/20 3:14 AM, Damien Le Moal wrote: > Document the device tree bindings for the Kendryte K210 SoC Fully > Programmable IO Array (FPIOA) pinctrl driver in > Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ > 1 file changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > new file mode 100644 > index 000000000000..8730add88ee0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > @@ -0,0 +1,106 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings > + > +maintainers: > + - Damien Le Moal <damien.lemoal@wdc.com> > + > +description: > + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging > + any of 256 possible functions to any of 48 IO pins. Pin function configuration > + is performed on a per-pin basis. > + > +properties: > + compatible: > + const: kendryte,k210-fpioa > + > + reg: > + description: FPIOA controller register space base address and size > + > + clocks: > + minItems: 2 > + maxItems: 2 > + items: > + - description: Controller reference clock source > + - description: APB interface clock source > + > + clock-names: > + minItems: 2 > + maxItems: 2 > + items: > + - const: ref > + - const: pclk > + > + resets: > + maxItems: 1 > + > + kendryte,sysctl: > + minItems: 1 > + maxItems: 1 > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + phandle to the system controller node > + > + kendryte,power-offset: > + minItems: 1 > + maxItems: 1 > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Offset of the power domain control register of the system controller. > + The value should be the macro K210_SYSCTL_POWER_SEL defined in > + dt-bindings/mfd/k210-sysctl.h. > + > +patternProperties: > + '^.*$': > + if: > + type: object > + then: > + patternProperties: > + "^pinmux$": > + $ref: /schemas/pinctrl/pincfg-node.yaml > + description: > + An array of IO pins alternate functions. The values for each > + IO pin is a combination of an IO pin number (0 to 47) with the > + desired function for the IO pin. Functions are defined as macros in > + dt-bindings/pinctrl/k210-pinctrl.h. The K210_FPIOA(IO pin, function) > + is provided to facilitate the combination of IO pin numbers and > + functions. > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + - kendryte,sysctl > + - kendryte,power-offset > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/pinctrl/k210-pinctrl.h> > + #include <dt-bindings/mfd/k210-sysctl.h> > + #include <dt-bindings/clock/k210-sysctl.h> > + #include <dt-bindings/reset/k210-sysctl.h> > + > + fpioa: pinmux@502B0000 { > + compatible = "kendryte,k210-fpioa"; > + reg = <0x502B0000 0x100>; > + clocks = <&sysclk K210_CLK_FPIOA>; > + resets = <&sysrst K210_RST_FPIOA>; > + kendryte,sysctl = <&sysctl>; > + kendryte,power-offset = <K210_SYSCTL_POWER_SEL>; > + pinctrl-0 = <&fpioa_jtag>; > + pinctrl-names = "default"; > + > + fpioa_jtag: jtag { > + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, > + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, > + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, > + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; > + }; > + }; > Reviewed-by: Sean Anderson <seanga2@gmail.com>
On Sat, 07 Nov 2020 17:14:12 +0900, Damien Le Moal wrote: > Document the device tree bindings for the Kendryte K210 SoC Fully > Programmable IO Array (FPIOA) pinctrl driver in > Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ > 1 file changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml: properties:clocks:minItems: False schema does not allow 2 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml: properties:clocks:maxItems: False schema does not allow 2 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml: properties:clock-names:minItems: False schema does not allow 2 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml: properties:clock-names:maxItems: False schema does not allow 2 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml: ignoring, error in schema: properties: clocks: minItems warning: no schema found in file: ./Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.example.dts:19:18: fatal error: dt-bindings/pinctrl/k210-pinctrl.h: No such file or directory 19 | #include <dt-bindings/pinctrl/k210-pinctrl.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1364: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1396081 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: > Document the device tree bindings for the Kendryte K210 SoC Fully > Programmable IO Array (FPIOA) pinctrl driver in > Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ > 1 file changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > new file mode 100644 > index 000000000000..8730add88ee0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > @@ -0,0 +1,106 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings > + > +maintainers: > + - Damien Le Moal <damien.lemoal@wdc.com> > + > +description: > + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging > + any of 256 possible functions to any of 48 IO pins. Pin function configuration > + is performed on a per-pin basis. > + > +properties: > + compatible: > + const: kendryte,k210-fpioa > + > + reg: > + description: FPIOA controller register space base address and size > + > + clocks: > + minItems: 2 > + maxItems: 2 Can drop these. Implied by 'items' length. > + items: > + - description: Controller reference clock source > + - description: APB interface clock source > + > + clock-names: > + minItems: 2 > + maxItems: 2 > + items: > + - const: ref > + - const: pclk > + > + resets: > + maxItems: 1 > + > + kendryte,sysctl: > + minItems: 1 > + maxItems: 1 > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + phandle to the system controller node > + > + kendryte,power-offset: > + minItems: 1 > + maxItems: 1 > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: | > + Offset of the power domain control register of the system controller. Sounds like you should be using power-domains binding. > + The value should be the macro K210_SYSCTL_POWER_SEL defined in > + dt-bindings/mfd/k210-sysctl.h. > + > +patternProperties: > + '^.*$': > + if: > + type: object > + then: This is a hack for existing bindings. Use '-pins$' for the node names. > + patternProperties: > + "^pinmux$": Not really a pattern. > + $ref: /schemas/pinctrl/pincfg-node.yaml This is at the wrong level. Goes up 1 level. > + description: > + An array of IO pins alternate functions. The values for each > + IO pin is a combination of an IO pin number (0 to 47) with the > + desired function for the IO pin. Functions are defined as macros in > + dt-bindings/pinctrl/k210-pinctrl.h. The K210_FPIOA(IO pin, function) > + is provided to facilitate the combination of IO pin numbers and > + functions. > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + - kendryte,sysctl > + - kendryte,power-offset > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/pinctrl/k210-pinctrl.h> > + #include <dt-bindings/mfd/k210-sysctl.h> > + #include <dt-bindings/clock/k210-sysctl.h> > + #include <dt-bindings/reset/k210-sysctl.h> > + > + fpioa: pinmux@502B0000 { > + compatible = "kendryte,k210-fpioa"; > + reg = <0x502B0000 0x100>; > + clocks = <&sysclk K210_CLK_FPIOA>; > + resets = <&sysrst K210_RST_FPIOA>; > + kendryte,sysctl = <&sysctl>; > + kendryte,power-offset = <K210_SYSCTL_POWER_SEL>; > + pinctrl-0 = <&fpioa_jtag>; > + pinctrl-names = "default"; > + > + fpioa_jtag: jtag { > + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, > + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, > + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, > + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; > + }; > + }; > -- > 2.28.0 >
On 11/9/20 10:36 AM, Rob Herring wrote: > On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: >> Document the device tree bindings for the Kendryte K210 SoC Fully >> Programmable IO Array (FPIOA) pinctrl driver in >> Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >> >> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> >> --- >> .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ >> 1 file changed, 106 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >> new file mode 100644 >> index 000000000000..8730add88ee0 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >> @@ -0,0 +1,106 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings >> + >> +maintainers: >> + - Damien Le Moal <damien.lemoal@wdc.com> >> + >> +description: >> + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging >> + any of 256 possible functions to any of 48 IO pins. Pin function configuration >> + is performed on a per-pin basis. >> + >> +properties: >> + compatible: >> + const: kendryte,k210-fpioa >> + >> + reg: >> + description: FPIOA controller register space base address and size >> + >> + clocks: >> + minItems: 2 >> + maxItems: 2 > > Can drop these. Implied by 'items' length. > >> + items: >> + - description: Controller reference clock source >> + - description: APB interface clock source >> + >> + clock-names: >> + minItems: 2 >> + maxItems: 2 >> + items: >> + - const: ref >> + - const: pclk >> + >> + resets: >> + maxItems: 1 >> + >> + kendryte,sysctl: >> + minItems: 1 >> + maxItems: 1 >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + description: | >> + phandle to the system controller node >> + >> + kendryte,power-offset: >> + minItems: 1 >> + maxItems: 1 >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: | >> + Offset of the power domain control register of the system controller. > > Sounds like you should be using power-domains binding. This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. --Sean > >> + The value should be the macro K210_SYSCTL_POWER_SEL defined in >> + dt-bindings/mfd/k210-sysctl.h. >> + >> +patternProperties: >> + '^.*$': >> + if: >> + type: object >> + then: > > This is a hack for existing bindings. Use '-pins$' for the node names. > >> + patternProperties: >> + "^pinmux$": > > Not really a pattern. > >> + $ref: /schemas/pinctrl/pincfg-node.yaml > > This is at the wrong level. Goes up 1 level. > >> + description: >> + An array of IO pins alternate functions. The values for each >> + IO pin is a combination of an IO pin number (0 to 47) with the >> + desired function for the IO pin. Functions are defined as macros in >> + dt-bindings/pinctrl/k210-pinctrl.h. The K210_FPIOA(IO pin, function) >> + is provided to facilitate the combination of IO pin numbers and >> + functions. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - resets >> + - kendryte,sysctl >> + - kendryte,power-offset >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/pinctrl/k210-pinctrl.h> >> + #include <dt-bindings/mfd/k210-sysctl.h> >> + #include <dt-bindings/clock/k210-sysctl.h> >> + #include <dt-bindings/reset/k210-sysctl.h> >> + >> + fpioa: pinmux@502B0000 { >> + compatible = "kendryte,k210-fpioa"; >> + reg = <0x502B0000 0x100>; >> + clocks = <&sysclk K210_CLK_FPIOA>; >> + resets = <&sysrst K210_RST_FPIOA>; >> + kendryte,sysctl = <&sysctl>; >> + kendryte,power-offset = <K210_SYSCTL_POWER_SEL>; >> + pinctrl-0 = <&fpioa_jtag>; >> + pinctrl-names = "default"; >> + >> + fpioa_jtag: jtag { >> + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, >> + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, >> + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, >> + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; >> + }; >> + }; >> -- >> 2.28.0 >>
On Mon, Nov 9, 2020 at 9:45 AM Sean Anderson <seanga2@gmail.com> wrote: > > On 11/9/20 10:36 AM, Rob Herring wrote: > > On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: > >> Document the device tree bindings for the Kendryte K210 SoC Fully > >> Programmable IO Array (FPIOA) pinctrl driver in > >> Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> > >> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > >> --- > >> .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ > >> 1 file changed, 106 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> new file mode 100644 > >> index 000000000000..8730add88ee0 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> @@ -0,0 +1,106 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings > >> + > >> +maintainers: > >> + - Damien Le Moal <damien.lemoal@wdc.com> > >> + > >> +description: > >> + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging > >> + any of 256 possible functions to any of 48 IO pins. Pin function configuration > >> + is performed on a per-pin basis. > >> + > >> +properties: > >> + compatible: > >> + const: kendryte,k210-fpioa > >> + > >> + reg: > >> + description: FPIOA controller register space base address and size > >> + > >> + clocks: > >> + minItems: 2 > >> + maxItems: 2 > > > > Can drop these. Implied by 'items' length. > > > >> + items: > >> + - description: Controller reference clock source > >> + - description: APB interface clock source > >> + > >> + clock-names: > >> + minItems: 2 > >> + maxItems: 2 > >> + items: > >> + - const: ref > >> + - const: pclk > >> + > >> + resets: > >> + maxItems: 1 > >> + > >> + kendryte,sysctl: > >> + minItems: 1 > >> + maxItems: 1 > >> + $ref: /schemas/types.yaml#/definitions/phandle-array > >> + description: | > >> + phandle to the system controller node > >> + > >> + kendryte,power-offset: > >> + minItems: 1 > >> + maxItems: 1 > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + description: | > >> + Offset of the power domain control register of the system controller. > > > > Sounds like you should be using power-domains binding. > > This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. Okay, please make that clear in the description. You can combine the above 2 properties into one which is a phandle+offset. Rob
On 2020/11/11 23:32, Rob Herring wrote: > On Mon, Nov 9, 2020 at 9:45 AM Sean Anderson <seanga2@gmail.com> wrote: >> >> On 11/9/20 10:36 AM, Rob Herring wrote: >>> On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: >>>> Document the device tree bindings for the Kendryte K210 SoC Fully >>>> Programmable IO Array (FPIOA) pinctrl driver in >>>> Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >>>> >>>> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> >>>> --- >>>> .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ >>>> 1 file changed, 106 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >>>> new file mode 100644 >>>> index 000000000000..8730add88ee0 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >>>> @@ -0,0 +1,106 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings >>>> + >>>> +maintainers: >>>> + - Damien Le Moal <damien.lemoal@wdc.com> >>>> + >>>> +description: >>>> + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging >>>> + any of 256 possible functions to any of 48 IO pins. Pin function configuration >>>> + is performed on a per-pin basis. >>>> + >>>> +properties: >>>> + compatible: >>>> + const: kendryte,k210-fpioa >>>> + >>>> + reg: >>>> + description: FPIOA controller register space base address and size >>>> + >>>> + clocks: >>>> + minItems: 2 >>>> + maxItems: 2 >>> >>> Can drop these. Implied by 'items' length. >>> >>>> + items: >>>> + - description: Controller reference clock source >>>> + - description: APB interface clock source >>>> + >>>> + clock-names: >>>> + minItems: 2 >>>> + maxItems: 2 >>>> + items: >>>> + - const: ref >>>> + - const: pclk >>>> + >>>> + resets: >>>> + maxItems: 1 >>>> + >>>> + kendryte,sysctl: >>>> + minItems: 1 >>>> + maxItems: 1 >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + description: | >>>> + phandle to the system controller node >>>> + >>>> + kendryte,power-offset: >>>> + minItems: 1 >>>> + maxItems: 1 >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + description: | >>>> + Offset of the power domain control register of the system controller. >>> >>> Sounds like you should be using power-domains binding. >> >> This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. > > Okay, please make that clear in the description. You can combine the > above 2 properties into one which is a phandle+offset. Could you point me to an example of such property ? I am not sure how to do that so an example would help. Thanks. > > Rob >
On Wed, 2020-11-11 at 15:06 +0000, Damien Le Moal wrote: > On 2020/11/11 23:32, Rob Herring wrote: > > On Mon, Nov 9, 2020 at 9:45 AM Sean Anderson <seanga2@gmail.com> wrote: > > > > > > On 11/9/20 10:36 AM, Rob Herring wrote: > > > > On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: > > > > > Document the device tree bindings for the Kendryte K210 SoC Fully > > > > > Programmable IO Array (FPIOA) pinctrl driver in > > > > > Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > > > > > > > > > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > > > > > --- > > > > > .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ > > > > > 1 file changed, 106 insertions(+) > > > > > create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > > > > new file mode 100644 > > > > > index 000000000000..8730add88ee0 > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > > > > > @@ -0,0 +1,106 @@ > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > +%YAML 1.2 > > > > > +--- > > > > > +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > + > > > > > +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings > > > > > + > > > > > +maintainers: > > > > > + - Damien Le Moal <damien.lemoal@wdc.com> > > > > > + > > > > > +description: > > > > > + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging > > > > > + any of 256 possible functions to any of 48 IO pins. Pin function configuration > > > > > + is performed on a per-pin basis. > > > > > + > > > > > +properties: > > > > > + compatible: > > > > > + const: kendryte,k210-fpioa > > > > > + > > > > > + reg: > > > > > + description: FPIOA controller register space base address and size > > > > > + > > > > > + clocks: > > > > > + minItems: 2 > > > > > + maxItems: 2 > > > > > > > > Can drop these. Implied by 'items' length. > > > > > > > > > + items: > > > > > + - description: Controller reference clock source > > > > > + - description: APB interface clock source > > > > > + > > > > > + clock-names: > > > > > + minItems: 2 > > > > > + maxItems: 2 > > > > > + items: > > > > > + - const: ref > > > > > + - const: pclk > > > > > + > > > > > + resets: > > > > > + maxItems: 1 > > > > > + > > > > > + kendryte,sysctl: > > > > > + minItems: 1 > > > > > + maxItems: 1 > > > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > > > + description: | > > > > > + phandle to the system controller node > > > > > + > > > > > + kendryte,power-offset: > > > > > + minItems: 1 > > > > > + maxItems: 1 > > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > + description: | > > > > > + Offset of the power domain control register of the system controller. > > > > > > > > Sounds like you should be using power-domains binding. > > > > > > This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. > > > > Okay, please make that clear in the description. You can combine the > > above 2 properties into one which is a phandle+offset. > > Could you point me to an example of such property ? I am not sure how to do that > so an example would help. Thanks. Please ignore. Found what I need. Thanks. > > > > > Rob > > > >
Hi Damien, Sean, On Mon, Nov 9, 2020 at 4:46 PM Sean Anderson <seanga2@gmail.com> wrote: > On 11/9/20 10:36 AM, Rob Herring wrote: > > On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: > >> Document the device tree bindings for the Kendryte K210 SoC Fully > >> Programmable IO Array (FPIOA) pinctrl driver in > >> Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> > >> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >> + kendryte,power-offset: > >> + minItems: 1 > >> + maxItems: 1 > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + description: | > >> + Offset of the power domain control register of the system controller. > > > > Sounds like you should be using power-domains binding. > > This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. Which brings to my attention the power-source property is not documented below... > >> + The value should be the macro K210_SYSCTL_POWER_SEL defined in > >> + dt-bindings/mfd/k210-sysctl.h. > >> + > >> +patternProperties: > >> + '^.*$': > >> + if: > >> + type: object > >> + then: As the driver supports e.g. bias and drive-strength, these should be documented here, too. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 2020/11/19 19:58, Geert Uytterhoeven wrote: > Hi Damien, Sean, > > On Mon, Nov 9, 2020 at 4:46 PM Sean Anderson <seanga2@gmail.com> wrote: >> On 11/9/20 10:36 AM, Rob Herring wrote: >>> On Sat, Nov 07, 2020 at 05:14:12PM +0900, Damien Le Moal wrote: >>>> Document the device tree bindings for the Kendryte K210 SoC Fully >>>> Programmable IO Array (FPIOA) pinctrl driver in >>>> Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml >>>> >>>> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml > >>>> + kendryte,power-offset: >>>> + minItems: 1 >>>> + maxItems: 1 >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + description: | >>>> + Offset of the power domain control register of the system controller. >>> >>> Sounds like you should be using power-domains binding. >> >> This is for pin power domains. E.g. pins 0-5 can be set to 1V8 or 3V3 logic levels. > > Which brings to my attention the power-source property is not > documented below... > >>>> + The value should be the macro K210_SYSCTL_POWER_SEL defined in >>>> + dt-bindings/mfd/k210-sysctl.h. >>>> + >>>> +patternProperties: >>>> + '^.*$': >>>> + if: >>>> + type: object >>>> + then: > > As the driver supports e.g. bias and drive-strength, these should be > documented here, too. Thanks for the review. I fixed everything today and ran everything through "make dt_binding_check". Will send a V2 series tomorrow after some more fixes and tests. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds >
diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml new file mode 100644 index 000000000000..8730add88ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings + +maintainers: + - Damien Le Moal <damien.lemoal@wdc.com> + +description: + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging + any of 256 possible functions to any of 48 IO pins. Pin function configuration + is performed on a per-pin basis. + +properties: + compatible: + const: kendryte,k210-fpioa + + reg: + description: FPIOA controller register space base address and size + + clocks: + minItems: 2 + maxItems: 2 + items: + - description: Controller reference clock source + - description: APB interface clock source + + clock-names: + minItems: 2 + maxItems: 2 + items: + - const: ref + - const: pclk + + resets: + maxItems: 1 + + kendryte,sysctl: + minItems: 1 + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + phandle to the system controller node + + kendryte,power-offset: + minItems: 1 + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset of the power domain control register of the system controller. + The value should be the macro K210_SYSCTL_POWER_SEL defined in + dt-bindings/mfd/k210-sysctl.h. + +patternProperties: + '^.*$': + if: + type: object + then: + patternProperties: + "^pinmux$": + $ref: /schemas/pinctrl/pincfg-node.yaml + description: + An array of IO pins alternate functions. The values for each + IO pin is a combination of an IO pin number (0 to 47) with the + desired function for the IO pin. Functions are defined as macros in + dt-bindings/pinctrl/k210-pinctrl.h. The K210_FPIOA(IO pin, function) + is provided to facilitate the combination of IO pin numbers and + functions. + +required: + - compatible + - reg + - clocks + - resets + - kendryte,sysctl + - kendryte,power-offset + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/k210-pinctrl.h> + #include <dt-bindings/mfd/k210-sysctl.h> + #include <dt-bindings/clock/k210-sysctl.h> + #include <dt-bindings/reset/k210-sysctl.h> + + fpioa: pinmux@502B0000 { + compatible = "kendryte,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>; + resets = <&sysrst K210_RST_FPIOA>; + kendryte,sysctl = <&sysctl>; + kendryte,power-offset = <K210_SYSCTL_POWER_SEL>; + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + + fpioa_jtag: jtag { + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; + }; + };
Document the device tree bindings for the Kendryte K210 SoC Fully Programmable IO Array (FPIOA) pinctrl driver in Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml