| Message ID | 20201107081420.60325-18-damien.lemoal@wdc.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | RISC-V Kendryte K210 support improvments | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On 11/7/20 3:14 AM, Damien Le Moal wrote: > Introduce the dt-bindings file include/dt-bindings/reset/k210_sysctl.h > to define IDs for all 30 reset signals available on the Kendryte K210 > RISC-V SoC. > > Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> > --- > include/dt-bindings/reset/k210-rst.h | 42 ++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 include/dt-bindings/reset/k210-rst.h > > diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h > new file mode 100644 > index 000000000000..883c1aed50e8 > --- /dev/null > +++ b/include/dt-bindings/reset/k210-rst.h > @@ -0,0 +1,42 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> > + * Copyright (c) 2020 Western Digital Corporation or its affiliates. > + */ > +#ifndef RESET_K210_SYSCTL_H > +#define RESET_K210_SYSCTL_H > + > +/* > + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. > + * Taken from Kendryte SDK (kendryte-standalone-sdk). > + */ > +#define K210_RST_ROM 0 > +#define K210_RST_DMA 1 > +#define K210_RST_AI 2 > +#define K210_RST_DVP 3 > +#define K210_RST_FFT 4 > +#define K210_RST_GPIO 5 > +#define K210_RST_SPI0 6 > +#define K210_RST_SPI1 7 > +#define K210_RST_SPI2 8 > +#define K210_RST_SPI3 9 > +#define K210_RST_I2S0 10 > +#define K210_RST_I2S1 11 > +#define K210_RST_I2S2 12 > +#define K210_RST_I2C0 13 > +#define K210_RST_I2C1 14 > +#define K210_RST_I2C2 15 > +#define K210_RST_UART1 16 > +#define K210_RST_UART2 17 > +#define K210_RST_UART3 18 > +#define K210_RST_AES 19 > +#define K210_RST_FPIOA 20 > +#define K210_RST_TIMER0 21 > +#define K210_RST_TIMER1 22 > +#define K210_RST_TIMER2 23 > +#define K210_RST_WDT0 24 > +#define K210_RST_WDT1 25 > +#define K210_RST_SHA 26 > +#define K210_RST_RTC 29 > + > +#endif /* RESET_K210_SYSCTL_H */ > Reviewed-by: Sean Anderson <seanga2@gmail.com>
diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */
Introduce the dt-bindings file include/dt-bindings/reset/k210_sysctl.h to define IDs for all 30 reset signals available on the Kendryte K210 RISC-V SoC. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> --- include/dt-bindings/reset/k210-rst.h | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/dt-bindings/reset/k210-rst.h