| Message ID | 20201105171535.923570-2-gregory.clement@bootlin.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Extend irqchip ocelot driver to support other SoCs | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Thu, Nov 05, 2020 at 06:15:30PM +0100, Gregory CLEMENT wrote: > Add the Device Tree binding documentation for the Microsemi Luton > interrupt controller that is part of the ICPU. It is connected directly to > the MIPS core interrupt controller. > > Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> > --- > .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) The patches look fine, but can you convert this to schema first. > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt > index f5baeccb689f..94dc95cb815c 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt > @@ -1,8 +1,10 @@ > Microsemi Ocelot SoC ICPU Interrupt Controller > > +Luton belongs the same family of Ocelot: the VCoreIII family > + > Required properties: > > -- compatible : should be "mscc,ocelot-icpu-intr" > +- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr" > - reg : Specifies base physical address and size of the registers. > - interrupt-controller : Identifies the node as an interrupt controller > - #interrupt-cells : Specifies the number of cells needed to encode an > -- > 2.28.0 >
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt index f5baeccb689f..94dc95cb815c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -1,8 +1,10 @@ Microsemi Ocelot SoC ICPU Interrupt Controller +Luton belongs the same family of Ocelot: the VCoreIII family + Required properties: -- compatible : should be "mscc,ocelot-icpu-intr" +- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an
Add the Device Tree binding documentation for the Microsemi Luton interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)