| Message ID | 20201105135211.7160-1-georgi.djakov@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Thu, 05 Nov 2020 15:52:09 +0200, Georgi Djakov wrote: > The QUP ports exist in the topology, but are not exposed as an > endpoints in DT. Fix this by creating IDs and attach them to their > NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able > to request their interconnect paths and scale their bandwidth. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > --- > include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Thu 05 Nov 07:52 CST 2020, Georgi Djakov wrote: > The QUP nodes are currently defined just as entries in the topology, > but they are not referenced by any of the NoCs. Let's fix this and > "attach" them to their NoCs, so that the QUP drivers are able to use > them as path endpoints and scale their bandwidth. > > This is based on the information from the downstream msm-4.9 kernel. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Georgi, would you mind if I take the series through my tree, to avoid conflicts in sdm845.dtsi? Regards, Bjorn > --- > drivers/interconnect/qcom/sdm845.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c > index 5304aea3b058..366870150cbd 100644 > --- a/drivers/interconnect/qcom/sdm845.c > +++ b/drivers/interconnect/qcom/sdm845.c > @@ -177,6 +177,7 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); > > static struct qcom_icc_bcm *aggre1_noc_bcms[] = { > &bcm_sn9, > + &bcm_qup0, > }; > > static struct qcom_icc_node *aggre1_noc_nodes[] = { > @@ -190,6 +191,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { > [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, > [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, > [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, > + [MASTER_QUP_1] = &qhm_qup1, > }; > > static const struct qcom_icc_desc sdm845_aggre1_noc = { > @@ -218,6 +220,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { > [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, > [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, > [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, > + [MASTER_QUP_2] = &qhm_qup2, > }; > > static const struct qcom_icc_desc sdm845_aggre2_noc = {
On Thu 05 Nov 07:52 CST 2020, Georgi Djakov wrote: > The QUP ports exist in the topology, but are not exposed as an > endpoints in DT. Fix this by creating IDs and attach them to their > NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able > to request their interconnect paths and scale their bandwidth. > > Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > --- > include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h > index 290be38f40e6..67b500e24915 100644 > --- a/include/dt-bindings/interconnect/qcom,sdm845.h > +++ b/include/dt-bindings/interconnect/qcom,sdm845.h > @@ -19,6 +19,7 @@ > #define SLAVE_A1NOC_SNOC 7 > #define SLAVE_SERVICE_A1NOC 8 > #define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 > +#define MASTER_QUP_1 10 > > #define MASTER_A2NOC_CFG 0 > #define MASTER_QDSS_BAM 1 > @@ -32,6 +33,7 @@ > #define SLAVE_A2NOC_SNOC 9 > #define SLAVE_ANOC_PCIE_SNOC 10 > #define SLAVE_SERVICE_A2NOC 11 > +#define MASTER_QUP_2 12 > > #define MASTER_SPDM 0 > #define MASTER_TIC 1
On 11/11/20 06:37, Bjorn Andersson wrote: > On Thu 05 Nov 07:52 CST 2020, Georgi Djakov wrote: > >> The QUP nodes are currently defined just as entries in the topology, >> but they are not referenced by any of the NoCs. Let's fix this and >> "attach" them to their NoCs, so that the QUP drivers are able to use >> them as path endpoints and scale their bandwidth. >> >> This is based on the information from the downstream msm-4.9 kernel. >> >> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > Georgi, would you mind if I take the series through my tree, to avoid > conflicts in sdm845.dtsi? Agree. Please take it through your tree. Thanks, Georgi
diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h index 290be38f40e6..67b500e24915 100644 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -19,6 +19,7 @@ #define SLAVE_A1NOC_SNOC 7 #define SLAVE_SERVICE_A1NOC 8 #define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +#define MASTER_QUP_1 10 #define MASTER_A2NOC_CFG 0 #define MASTER_QDSS_BAM 1 @@ -32,6 +33,7 @@ #define SLAVE_A2NOC_SNOC 9 #define SLAVE_ANOC_PCIE_SNOC 10 #define SLAVE_SERVICE_A2NOC 11 +#define MASTER_QUP_2 12 #define MASTER_SPDM 0 #define MASTER_TIC 1
The QUP ports exist in the topology, but are not exposed as an endpoints in DT. Fix this by creating IDs and attach them to their NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able to request their interconnect paths and scale their bandwidth. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> --- include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++ 1 file changed, 2 insertions(+)